RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard Katz Head Grunt Office of Logic Design Igor Kleyner Deputy Grunt Office of Logic.
Download ReportTranscript RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard Katz Head Grunt Office of Logic Design Igor Kleyner Deputy Grunt Office of Logic.
RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard Katz Head Grunt Office of Logic Design Igor Kleyner Deputy Grunt Office of Logic Design September 8th, 2004 Background Background In 2003, some customers reported clusters of failures Customer failures had some common factors Stressful designs I/O and/or power supplies exceeding datasheet limits Failures occur early in device life Actel investigation indicated isolated programmed antifuses were failing to a higher impedance state Industry investigation Actel working closely with Industry Tiger Team (ITT) led by The Aerospace Corp. Participants include Lockheed Martin, Boeing, General Dynamics, Northrop Grumman Space Technology, JPL, NASA A series of experiments are being conducted to investigate the customer failures Remainder of presentation describes the two different Test Vehicles being used for the following experiments Industry Tiger Team Design NASA Test Design MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 2 Industry Tiger Team Design Top Level Block Diagram zoom_sel_n zoom[1:0] 1,146 Stage Slow Ring Oscillator 2 delay_out ResetSyncD Reset_n Set_n Clksel[2:0] Clk_ext ShiftFreq[1:0] A_Pattern_type A_Pattern_length[2:0] 707 Bit Array Shift Register 3 2 3 A_Monitor OE Clk_o_sel A0S B1 S IO_Pattern_type IO_Pattern_length[2:0] TOG_n 140 Bit I/O Shift Register 3 IO_pin[1] MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Freq_out IO_Monitor IO_pin[139] Wednesday, September 8th, 2004 3 Industry Tiger Team Design 1,146 Stage Slow Ring Oscillator ResetSyncD zoom[1] zoom[0] Monitor zoom_sel_n S A0 D B1 S S A0 SET CLR Q Delay_out Q B1 S 0 1 2 3 S A0 B1 S R-Cell CLR has priority over SET ResetSyncD Delay Line TPDL Delay_out Delay Line TPDH Synchronized Reset input assures clean startup of slow ring oscillator Delta Read & Record must be done via frequency measurement No mechanism to break ring and measure delay directly Zoom Debug feature Allows for enhanced isolation of delays during debug only Long oscillator frequency stabilization time of ~15 minutes at startup MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 4 Industry Tiger Team Design Slow Oscillator Startup MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 5 Industry Tiger Team Design 140 Bit I/O Shift Register I/O Reset Block IO_SetSyncD Set_n Startup Synchronizer Reset_n 3 Clksel[2:0] Clk_ext IO_Clock 2 ShiftFreq[1:0] IO_Pattern_length[2:0] IO_Pattern_type 50MHz Ring Oscillator D=0 IO_ResetSyncD Shift Enable Control IO_Shift_enable_n Monitor 3 Pattern Generator I/O Weave Shift Register Serial Pattern Checker IO_Monitor Monitor Pin Behavior Startup Test OK Error Independent controls to set Pattern generator toggle rate for internal R-Cells 16 unique patterns possible, with range of toggle rates (more later) Clock generated via internal 15 stage ring oscillator (~50MHz) Dedicated Startup Synchronization circuitry for IO_clock domain IO_Monitor indicates pass/fail On-chip self-checking circuitry detects and latches detected errors Note: not all errors are detectable by self-test MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 6 Industry Tiger Team Design Ring Oscillator Optional Buffer: D = 1 installed D = 0 do not install Clk_ext U1 U2 U14 U15 1 0 S D Q CLKINT 2 E Clock_out CLR D Q 4 E CLR D Q 8 E CLR D Q 16 E CLR D Q 32 Sliding Decoder E CLR D Q 64 E CLR Reset_n clksel[2] clksel[1] clksel[0] Division ClkSel[2:0] Factor 000 001 010 011 100 101 110 111 na 2 2 4 1 16 32 64 Approximate Frequency (MHz) Clk_ext 25.00 25.00 12.50 50.00 3.13 1.56 0.78 Ring Oscillator instantiated twice 1st drives Array SR, 2nd drives I/O SR Additional delay stage inserted in Array oscillator to keep two oscillators out of sync Ring Oscillators frequency dependent on Temperature & VCCA voltage Ring Oscillators NOT recommended for flight designs MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 7 Industry Tiger Team Design Shift Enable Control Independent Shift Enable circuits instantiated in each of the 2 sequential blocks to pace R-Cell toggling ShiftEnable_n 0 0 ShiftEnable_n fanout = 16 R-Cell U0 fan out managed via register replication 2 ShiftFreq 0 1 2 3 Clock A B C D 1 2 3 U0 D Q D SET Q D SET Q SET D Q CLR U1 U2 U3 Both Array shift register & ResetSyncD I/O shift register blocks set by same input configuration pin settings: Clock ResetSyncD If ShiftFreq==00: Every Cycle ShiftEnable_n If ShiftFreq==01: Every 2nd Cycle ShiftEnable_n If ShiftFreq==10: Every 3rd Cycle ShiftEnable_n If ShiftFreq==11: Every 4th Cycle ShiftEnable_n Asserted active low enable is consistent with SX-A/S R-CELL enable polarity MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 8 Industry Tiger Team Design Pattern Generator SetSyncD 0 Serial_Feedback Pattern_Length[2:0] 1 2 4 3 5 6 7 0 1 3 4 5 6 7 01 2 3 D E SET CLR Q D E SET Q CLR D E SET Q CLR D E SET Q D E CLR SET Q CLR D E SET CLR Q D E SET CLR Q D E SET CLR Q D E SET Q Serial_Pattern CLR Pattern_type Clock ResetSyncD ShiftEnable_n Pattern Pattern Type Length 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Code Length 1 0 0 1 1 0 0 0 1 0 0 0 1 One hot I/O at a time switching 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 Wave of 0's followed by wave of 1 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles in entire I/O ring 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1's 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 Paper #172 2 3 #Bits+9 5 6 7 8 9 2 3 #Bits+9 5 6 7 8 9 Switching Bits Rate 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 Wednesday, September 8th, 2004 100.00% 66.67% N/A 40.00% 33.33% 28.57% 25.00% 22.22% 50.00% 33.33% N/A 20.00% 16.67% 14.29% 12.50% 11.11% 9 Industry Tiger Team Design I/O Weave Shift Register I/O Weave block three modes of operation Mode 1: I/O Bypass (OE=‘0’ TOG_n=‘X’) Operates as shift register bypassing the I/Os thru 2-1 multiplexers No I/Os toggle and are tri-stated Middle Cell #I/Os - 2 First Cell Used Once I/Os placed sequentially around device in order of shift register Middle Cell #I/Os - 2 Last Cell Used Once IO_SetSyncD IO_Serial_Pattern 1 0 1 S D SET Q S E CLR S 1 0 S 0 1 S D SET Q S Q E CLR S 1 0 S 0 1 S D SET Q S Q E CLR Q S 1 0 S 0 1 S D SET Q S E CLR Q S 1 0 S 0 S D SET Q IO_Feedback S E CLR Q IO_Clock IO_ShiftEnable_n IO_ResetSyncD TOG_n OE MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 10 Industry Tiger Team Design I/O Weave Shift Register I/O Weave block three modes of operation Mode 2: I/O Weave (OE=‘1’ TOG_n=‘1’) Operates as shift register toggling I/O pad at pattern generator defined rate Signal takes path thru output buffer to the pad and back into input buffer I/O toggle rate controlled by Pattern Generator Middle Cell #I/Os - 2 First Cell Used Once I/Os placed sequentially around device in order of shift register Middle Cell #I/Os - 2 Last Cell Used Once IO_SetSyncD IO_Serial_Pattern 1 0 1 S D SET Q S E CLR S 1 0 S 0 1 S D SET Q S Q E CLR S 1 0 S 0 1 S D SET Q S Q E CLR Q S 1 0 S 0 1 S D SET Q S E CLR Q S 1 0 S 0 S D SET Q IO_Feedback S E CLR Q IO_Clock IO_ShiftEnable_n IO_ResetSyncD TOG_n OE MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 11 Industry Tiger Team Design I/O Weave Shift Register I/O Weave block three modes of operation Mode 3: All I/O Toggle (OE=‘1’ TOG_n=‘0’) Simultaneously switches all I/Os from 0 to 1 then 1 to 0 Pattern follows shift register chain enabling pattern checker to detect errors at any point in chain Simultaneous 100% I/O Toggle Rate Register n+1 <= !n Middle Cell #I/Os - 2 First Cell Used Once I/Os placed sequentially around device in order of shift register Middle Cell #I/Os - 2 Last Cell Used Once IO_SetSyncD IO_Serial_Pattern 1 0 1 S D SET Q S E CLR S 1 0 S 0 1 S D SET Q S Q E CLR S 1 0 S 0 1 S D SET Q S Q E CLR Q S 1 0 S 0 1 S D SET Q S E CLR Q S 1 0 S 0 S D SET Q IO_Feedback S E CLR Q IO_Clock IO_ShiftEnable_n IO_ResetSyncD TOG_n OE MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 12 Industry Tiger Team Design 707 Bit Array Shift Register Array Reset Block A_SetSyncD Set_n Startup Synchronizer Reset_n 3 Clksel[2:0] Clk_ext A_Clock 2 ShiftFreq[1:0] A_Pattern_length[2:0] A_Pattern_type 50MHz Ring Oscillator D=1 A_ResetSyncD Shift Enable Control A_Shift_enable_n Monitor 3 Pattern Generator Array Shift Register 707 R-Cells Serial Pattern Checker A_Monitor Monitor Pin Behavior Array shift register has independent controls to set Pattern generator toggle rate for internal R-Cells Startup Test OK Error Options for the Pattern Generator identical to I/O Shift Register Pattern Generator Typical setting for Simultaneous Switching Registers (SSR) set at 12.5% Clock generated via internal 16 stage ring oscillator (~50MHz) Dedicated Startup Synchronization circuitry for A_Clock domain A_Monitor indicates pass/fail On-chip self-checking circuitry detects and latches detected errors Note: not all errors are detectable by this self-test MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 13 Industry Tiger Team Design Aerospace Experiments Colonel Test RT54SX32S MEC with “old” algo Project 4b1 Temp = ~40°C VCCA= 2.5V Project 7 ~500 parts Temp = ~40°C VCCA= 2.5V 600 hrs Project 4b2 Temp = ~40°C VCCA= 2.5V 1000 hrs + RT54SX32S MEC with “new” algo General Test 330 parts Project 4b2 Temp = ~40°C VCCA= 2.5V RT54SX32S MEC with “old” algo 83 parts Project 4b2 83 parts Temp = 85°C VCCA= 3.0V 1000 hrs + MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 14 NASA Design Top Level Block Diagram delay_in delay_sel_n[1:0] 1,236 Stage Delay Line 2 delay_out ResetSyncD Reset_n Set_n CLKA ShiftFreq[1:0] A_Pattern_type A_Pattern_length[2:0] 621 Bit Array Shift Register 2 3 A_Monitor Array_out OE HCLK IO_Pattern_type IO_Pattern_length[2:0] TOG_n 144 Bit I/O Shift Register 3 IO_pin[1] MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 IO_Monitor IO_pin[143] Wednesday, September 8th, 2004 15 NASA Design Header Bd. Clock & Reset Driver NASA Office of Logic Design (OLD) designed and built solder in card to Burn-in Board (BIB) to provide clock and reset to 8 Devices Under Test (DUT) Card solders into BIB configuration socket locations Clocks for DUTs in each column can be controlled to run 180° out of phase Clocks can be driven up to 64MHz Jumper selectable clock dividers available on Header Board HCLK, CLKA, and CLKB frequency independently settable MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 16 NASA Design 1,236 Stage Delay Line delay_sel_n[0] delay_sel_n[1] 1,236 NAND4 gate Delay Line Sliding Decoder Monitor D Q D Q D Q D Q HCLK E CLR E CLR E E CLR CLR ResetSyncD 2 Delay_in 8 128 D 0 1 2 3 SET CLR Q Delay_out Q R-Cell CLR has priority over SET Configuration lines select input to delay line during operation Synchronized Reset input insures clean startup Direct delay delta read & record measurement possible via Delay_in No free running oscillator & related self-heating thermal effects, therefore no startup stabilization issues Allows for more accurate delay measurements Zoom feature removed as un-needed, Action Probe circuitry sufficient for debug MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 17 NASA Design 144 Bit I/O Shift Register I/O Reset Block IO_SetSyncD Set_n Startup Synchronizer Reset_n IO_ResetSyncD HCLK 2 ShiftFreq[1:0] Shift Enable Control IO_Shift_enable_n Monitor 3 IO_Pattern_length[2:0] IO_Pattern_type Pattern Generator I/O Weave Shift Register Serial Pattern Checker IO_Monitor Monitor Pin Behavior Changes Startup Test OK Error Utilizes HCLK vs. 15 stage internal ring oscillator Industry Tiger Team design does NOT utilize the HCLK resource HCLK driven by NASA header board add-on card Dedicated Reset Synchronization circuitry for HCLK clock domain Increased fan out of Shift Register Enable nets from 16 vs. 29 Exceeds maximum fan out allowed (24) in Designer Software by 20% Number of I/Os 143 vs. 139 78 configured for 5V CMOS, remainder 5V TTL; Industry Tiger Team design all TTL MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 18 NASA Design 621 Bit Array Shift Register Array Reset Block A_SetSyncD Set_n Startup Synchronizer Reset_n A_ResetSyncD CLKA 2 ShiftFreq[1:0] A_Pattern_length[2:0] A_Pattern_type Shift Enable Control A_Shift_enable_n Monitor 3 Pattern Generator Array Shift Register 621 R-Cells Serial Pattern Checker A_Monitor Array_out Changes Utilizes CLKA vs. 16 stage internal ring oscillator CLKA driven by NASA header board add-on card Increased fan out of Shift Register Enable nets from 16 vs. 29 Exceeds maximum fan out allowed (24) in Designer Software by 20% Shift register R-Cells manually placed to improve utilization of Long Vertical Tracks (LVT) and Long Horizontal Tracks (LHT) Array_out added to increase observability at tester Number of bits 621 vs. 707 MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 19 NASA Design Final Design Summary Utilization Post-Combiner device utilization: SEQUENTIAL Used: 1080 Total: 1080 COMB Used: 1800 Total: 1800 LOGIC Used: 2880 Total: 2880 IO w/ Clocks Used: 168 Total: 170 CLOCK Used: 2 Total: 2 HCLOCK Used: 1 Total: 1 (100.00%) (100.00%) (100.00%) (seq+comb) (78 CMOS) (89 TTL) Fan out 23 nets have fan out of 29 1 net with fan out of 28 Timing Analysis Maximum frequency (@ 125C, VCCA = 2.25V, VCCI = 4.5V, Speed –1) Array Clk => 72MHz IO Clk => 71MHz Hold time analysis (@ -55C, VCCA = 2.75V, VCCI = 5.5V, Speed –1) Shortest path slack => 0.51ns NASA design bounds user applications better than Industry Tiger Team design MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 20 NASA Experiments Test Protocol RT54SX32S MEC “Modified New Algo” Parts to be tested in 500 hour steps Stress levels increased for each step. Voltage, # SSOs, amount of SSU, time Internal circuit loading fixed at 120% of max load Each step is 250 hours of HTOL followed by 250 hours of LTOL HOT 300 parts Project KH1 Temp = 125°C VCCA= 2.75V RTSX32SU UMC 300 parts RT54SX32S MEC “Modified New Algo” 250 hrs Increasing VCCA/VCCI Voltage Increasing SSO Increasing SSU Increased time COLD 300 parts Project KC1 Temp = -55°C VCCA= 2.75V RTSX32SU UMC 300 parts MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Increasing VCCA/VCCI Voltage Increasing SSO Increasing SSU Increased time 250 hrs Paper #172 Wednesday, September 8th, 2004 21 Appendix: RTSXS-U Test Data MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 22 ITT Design Actel RTSX-SU (UMC) Data set This data set includes the following for RTSXS-U: 2 sets of experiments were completed (P7, P4B2) RTOL = Room Temperature Operating Life TC = Temperature Cycle (-65°C to 150°C) Industry Tiger Team Design - Summary Product Number of units RTSX32S-U 366 RTSX72S-U 100 RTSX32S-U 198 Total RTSX32S-U RTSX72S-U 466 Total 136 Failures 0 0 68 68 0 Unit hours 104288 16800 33264 Type RTOL RTOL RTOL Expt P7 P7 P4B2* TC TC NA NA 154352 0 0 6800 6800 13600 * These 198 Units completed 168 hours of P7 before being put into the P4B2 configuration MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 23 ITT Design P7 Data Configuration Details: No I/O’s toggle, Array toggle rate = I/O toggle rate = 12.5% 3 monitor pins toggling - Visual readout using LED Undershoot less than -0.4V Industry Tiger Team Design - P7 Product Number of units RTSX32S-U 100 RTSX32S-U 266 RTSX72S-U 100 Total Failures 0 0 0 466 MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles #of hours 596 168 168 Unit hours 59600 44688 16800 Type RTOL RTOL RTOL 121088 Paper #172 Wednesday, September 8th, 2004 24 ITT Design P4B2 Data Configuration Details: I/O toggle rate = 50% (70 I/Os), Array toggle rate = 12.5% ~2V undershoot Industry Tiger Team Design - P4B2 Product Number of units RTSX32S-U 198* Total Failures 0 #of hours 168 198 Unit hours 33264 Type RTOL 33264 * These 198 Units completed 168 hours of P7 before being put into the P4B2 configuration MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 25 NASA/Actel Team NASA Igor Kleyner Rich Katz Actel Manish Babladi Marco Cheung Paul Louris Minal Sawant Dan Elftmann MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles Paper #172 Wednesday, September 8th, 2004 26