Transcript IC-UNICAMP Finite State Machines Mixed Style RTL Modeling Extraído da George Mason Univ. ECE 545 Lecture 5 MC 603/613 - 2006 1-1

IC-UNICAMP
Finite State Machines
Mixed Style RTL Modeling
Extraído da George Mason Univ.
ECE 545
Lecture 5
MC 603/613 - 2006
1-1
IC-UNICAMP
Finite State Machines (FSMs)
• Any Circuit with Memory Is a Finite State
Machine
– Even computers can be viewed as huge FSMs
• Design of FSMs Involves
– Defining states
– Defining transitions between states
– Optimization / minimization
• Above Approach Is Practical for Small FSMs
Only
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Máquina de Estados
IC-UNICAMP
Circuito Sequencial Síncrono Genérico
Máquina de Moore
Máquina de Mealy
X
CC
Si+1
FF
X
Si
CC
Saída Y muda apenas
na transição do clock
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Y
Y
CC
Si+1
FF
Si
Saída Y pode mudar em
qualquer instante, em
função da entrada X
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IC-UNICAMP
Mealy
entr / saída
Síntese de uma máquina de estados
S0
Moore
entr
S3
S1
Estado

Entradas
Atual
Próximo
S0
S2
S1
Saídas
S2
Diagrama de Transição de Estados
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Tabela de Transição de Estados
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Síntese de uma máquina de estados
IC-UNICAMP
Estado
Atual
Próximo
00
01
10
Entradas
Saídas
Codificação dos estados
• S0 = 00 etc
Equações booleanas dos circuitos combinacionais
• Si+1 = fS (Si, X)
• Y = fY (Si, X)
(em maq. de Moore, só S)
• Sintetizar os CCs
• Elementos de memória podem ser
FF-D ou FF-JK
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Moore FSM
IC-UNICAMP
• Output Is a Function of Present State Only
Inputs
Next State
function
Next State
clock
reset
Present State
Register
Output
function
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Present State
Outputs
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Mealy FSM
IC-UNICAMP
• Output Is a Function of a Present State and
Inputs
Inputs
Next State
function
Next State
clock
reset
Present State
Register
Output
function
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Present State
Outputs
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Moore Machine
IC-UNICAMP
transition
condition 1
state 1 /
output 1
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state 2 /
output 2
transition
condition 2
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Mealy Machine
IC-UNICAMP
transition condition 1 /
output 1
state 2
state 1
transition condition 2 /
output 2
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Moore vs. Mealy FSM (1)
IC-UNICAMP
• Moore and Mealy FSMs Can Be Functionally
Equivalent
– Equivalent Mealy FSM can be derived from Moore
FSM and vice versa
• Mealy FSM Has Richer Description and
Usually Requires Smaller Number of States
– Smaller circuit area
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Moore vs. Mealy FSM (2)
IC-UNICAMP
• Mealy FSM Computes Outputs as soon as
Inputs Change
– Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM
• Moore FSM Has No Combinational Path
Between Inputs and Outputs
– Moore FSM is more likely to have a shorter critical
path
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Moore FSM - Example 1
IC-UNICAMP
• Moore FSM that Recognizes Sequence “10”
0
1
S0 / 0
1
reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
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0
S1 / 0
0
S1: “1”
observed
1
S2 / 1
S2: “10”
observed
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Mealy FSM - Example 1
IC-UNICAMP
• Mealy FSM that Recognizes Sequence “10”
0/0
1/0
S0
reset
Meaning
of states:
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1/0
S1
0/1
S0: No
elements
of the
sequence
observed
S1: “1”
observed
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IC-UNICAMP
Moore & Mealy FSMs – Example 1
clock
0
1
0
0
0
S0
S1
S2
S0
S0
S0
S1
S0
S0
S0
input
Moore
Mealy
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FSMs in VHDL
IC-UNICAMP
• Finite State Machines Can Be Easily
Described With Processes
• Synthesis Tools Understand FSM Description
If Certain Rules Are Followed
• State transitions should be described in a process
sensitive to clock and asynchronous reset signals
only
• Outputs described as concurrent statements
outside the process
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Moore FSM
IC-UNICAMP
process(clock, reset)
Inputs
Next State
function
Next State
clock
reset
concurrent
statements
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Present State
Register
Present State
Output
function
Outputs
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Mealy FSM
IC-UNICAMP
process(clock, reset)
Inputs
Next State
function
Next State
clock
reset
concurrent
statements
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Present State
Present State
Register
Output
function
Outputs
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IC-UNICAMP
FSM States (1)
architecture behavior of FSM is
type state is (list of states);
signal FSM_state: state;
begin
process(clk, reset)
begin
if reset = ‘1’ then
FSM_state <= initial state;
elsif (clock = ‘1’ and clock’event) then
case FSM_state is
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FSM States (2)
IC-UNICAMP
case FSM_state is
when state_1 =>
if transition condition 1 then
FSM_state <= state_1;
end if;
when state_2 =>
if transition condition 2 then
FSM_state <= state_2;
end if;
end case;
end if; end process;
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Moore FSM - Example 1
IC-UNICAMP
• Moore FSM that Recognizes Sequence “10”
0
1
S0 / 0
reset
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1
0
S1 / 0
1
S2 / 1
0
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Moore FSM in VHDL (1)
IC-UNICAMP
TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Moore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Moore_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Moore_state <= S1;
ELSE
Moore_state <= S0;
END IF;
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IC-UNICAMP
Moore FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Moore_state <= S2;
ELSE
Moore_state <= S1;
END IF;
WHEN S2 =>
IF input = ‘0’ THEN
Moore_state <= S0;
ELSE
Moore_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
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Mealy FSM - Example 1
IC-UNICAMP
• Mealy FSM that Recognizes Sequence “10”
0/0
1/0
S0
reset
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1/0
S1
0/1
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IC-UNICAMP
Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);
SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)
BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
Mealy_state <= S0;
END IF;
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IC-UNICAMP
Mealy FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
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Moore FSM – Example 2: State diagram
IC-UNICAMP
resetn
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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Moore FSM – Example 2: State table
IC-UNICAMP
Next state
Present
state w = 0 w = 1
A
B
C
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A
A
A
B
C
C
Output
z
0
0
1
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Moore FSM
IC-UNICAMP
process(clock, reset)
Input: w
Next State
function
Next State
clock
resetn
concurrent
statements
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Present State
Register
Present State: y
Output
function
Output: z
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Moore FSM – Example 2: VHDL code (1)
IC-UNICAMP
USE ieee.std_logic_1164.all ;
ENTITY simple IS
PORT ( clock
resetn
w
z
END simple ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
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Moore FSM – Example 2: VHDL code (2)
IC-UNICAMP
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
WHEN C =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
END CASE ;
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Moore FSM – Example 2: VHDL code (3)
IC-UNICAMP
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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Moore FSM
IC-UNICAMP
process
Input: w
(w,
y_present)
process
(clock,
resetn)
concurrent
statements
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Next State
function
Next State: y_next
clock
resetn
Present State
Register
Output
function
Present State:
y_present
Output: z
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Alternative VHDL code (1)
IC-UNICAMP
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y_present, y_next : State_type ;
BEGIN
PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
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Alternative VHDL code (2)
IC-UNICAMP
WHEN C =>
IF w = '0' THEN
y_next <= A ;
ELSE
y_next <= C ;
END IF ;
END CASE ;
END PROCESS ;
PROCESS (clock, resetn)
BEGIN
IF resetn = '0' THEN
y_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
y_present <= y_next ;
END IF ;
END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ;
END Behavior ;
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Mealy FSM – Example 2: State diagram
IC-UNICAMP
resetn
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
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Mealy FSM – Example 2: State table
IC-UNICAMP
Next state
Output z
Present
state
w= 0
w= 1
w= 0
w= 1
A
B
A
A
B
B
0
0
0
1
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Mealy FSM
IC-UNICAMP
process(clock, reset)
Input: w
Next State
function
Next State
clock
resetn
concurrent
statements
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Present State: y
Present State
Register
Output
function
Output: z
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Mealy FSM – Example 2: VHDL code (1)
IC-UNICAMP
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Mealy IS
PORT ( clock : IN
resetn : IN
w
: IN
z
: OUT
END Mealy ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF Mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
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IC-UNICAMP
Mealy FSM – Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
END CASE ;
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IC-UNICAMP
Mealy FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
WITH y SELECT
z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
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