Transcript CS252 Graduate Computer Architecture Lecture 15 Caches I: 3 Cs and 7 ways to reduce misses October 25, 1999 Prof.

CS252
Graduate Computer Architecture
Lecture 15
Caches I:
3 Cs and 7 ways to reduce misses
October 25, 1999
Prof. John Kubiatowicz
10/25/00
CS252/Kubiatowicz
Lec 15.1
Review:
Genetic Programming for Design
• Genetic programming has two key aspects:
– An Encoding of the design space.
» This is a symbolic representation of the result space (genome).
» Much of the domain-specific knowledge and “art” involved here.
– A Reproduction strategy
» Includes a method for generating offspring from parents
Mutation: Changing random portions of an individual
Crossover: Merging aspects of two individuals
» Includes a method for evaluating the effectiveness (“fitness”) of
individual solutions.
• Generation of new branch predictors via genetic
programming:
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– Everything derived from a “basic” predictor (table) + simple
operators.
– Expressions arranged in a tree
– Mutation: random modification of node/replacement of subtree
– Crossover: swapping the subtrees of two parents.
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Lec 15.2
Review: Who Cares About the
Memory Hierarchy?
• Processor Only Thus Far in Course:
– CPU cost/performance, ISA, Pipelined Execution
CPU
CPU-DRAM Gap
“Moore’s Law”
100
10
1
“Less’ Law?”
µProc
60%/yr.
Processor-Memory
Performance Gap:
(grows 50% / year)
DRAM
DRAM
7%/yr.
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
Performance
1000
• 1980: no cache in µproc; 1995 2-level cache on chip
(1989 first Intel µproc with a cache on chip)
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Lec 15.3
Review: Memory Disambiguation
• Memory disambiguation buffer contains set of
active stores and loads in program order.
– Loads and stores are entered at issue time
– May not have addresses yet
• Optimistic dependence speculation: assume that
loads and stores don’t depend on each other
• Need disambiguation buffer to catch errors.
All checks occur at address resolution time:
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– When store address is ready, check for loads that are (1)
later in time and (2) have same address.
» These have been incorrectly speculated: flush and restart
– When load address is ready, check for stores that are (1)
earlier in time and (2) have same address
if (match) then
if (store value ready) then return value
else return pointer to reservation station
else
optimistically start load access
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Lec 15.4
Review: STORE sets
• Naïve speculation can cause problems for certain
load-store pairs.
• “Counter-Speculation”:
For each load, keep track of set of stores that
have forwarded information in past.
– If (prior store in store-set has unresolved address) then
wait for store address to be completed
else if (match) then
if (store value ready) then return value
else return pointer to reservation station
else
optimistically start load access
Store Set ID Table
(SSIT)
Last Fetched Store Table
(LFST)
Index
Load/Store PC
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SSID
Store Inum
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Lec 15.5
Processor-Memory
Performance Gap “Tax”
Processor
• Alpha 21164
• StrongArm SA110
• Pentium Pro
% Area
%Transistors
(cost)
(power)
37%
61%
64%
77%
94%
88%
– 2 dies per package: Proc/I$/D$ + L2$
• Caches have no inherent value,
only try to close performance gap
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Lec 15.6
What is a cache?
• Small, fast storage used to improve average access
time to slow memory.
• Exploits spacial and temporal locality
• In computer architecture, almost everything is a cache!
–
–
–
–
–
–
Registers a cache on variables
First-level cache a cache on second-level cache
Second-level cache a cache on memory
Memory a cache on disk (virtual memory)
TLB a cache on page table
Branch-prediction a cache on prediction information?
Proc/Regs
Bigger
L1-Cache
L2-Cache
Faster
Memory
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Disk, Tape, etc.
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Lec 15.7
Example: 1 KB Direct Mapped Cache
• For a 2 ** N byte cache:
– The uppermost (32 - N) bits are always the Cache Tag
– The lowest M bits are the Byte Select (Block Size = 2 ** M)
Block address
31
9
Cache Tag
Example: 0x50
4
0
Cache Index
Byte Select
Ex: 0x01
Ex: 0x00
Stored as part
of the cache “state”
Cache Tag
Cache Data
Byte 31
0x50
Byte 63
: :
Valid Bit
Byte 1
Byte 0
0
Byte 33 Byte 32 1
2
3
:
:
Byte 1023
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:
:
Byte 992 31
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Lec 15.8
Set Associative Cache
• N-way set associative: N entries for each Cache
Index
– N direct mapped caches operates in parallel
• Example: Two-way set associative cache
– Cache Index selects a “set” from the cache
– The two tags in the set are compared to the input in parallel
– Data is selected based on the tag result
Valid
Cache Tag
:
:
Adr Tag
Compare
Cache Data
Cache Index
Cache Data
Cache Block 0
Cache Block 0
:
:
Sel1 1
Mux
0 Sel0
Cache Tag
Valid
:
:
Compare
OR
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Hit
Cache Block
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Lec 15.9
Disadvantage of Set Associative Cache
• N-way Set Associative Cache versus Direct Mapped
Cache:
– N comparators vs. 1
– Extra MUX delay for the data
– Data comes AFTER Hit/Miss decision and set selection
• In a direct mapped cache, Cache Block is available
BEFORE Hit/Miss:
– Possible to assume a hit and continue. Recover later if miss.
Valid
Cache Tag
:
:
Adr Tag
Compare
Cache Data
Cache Index
Cache Data
Cache Block 0
Cache Block 0
:
:
Sel1 1
Mux
0 Sel0
Cache Tag
Valid
:
:
Compare
OR
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Hit
Cache Block
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Lec 15.10
Generations of Microprocessors
• Time of a full cache miss in instructions executed:
1st Alpha:
2nd Alpha:
3rd Alpha:
340 ns/5.0 ns = 68 clks x 2 or
266 ns/3.3 ns = 80 clks x 4 or
180 ns/1.7 ns =108 clks x 6 or
136
320
648
• 1/2X latency x 3X clock rate x 3X Instr/clock  5X
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Lec 15.11
What happens on a Cache miss?
• For in-order pipeline, 2 options:
– Freeze pipeline in Mem stage (popular early on: Sparc, R4000)
IF
ID
IF
EX
ID
Mem stall stall stall … stall Mem
Wr
EX stall stall stall … stall stall Ex Wr
– Use Full/Empty bits in registers + MSHR queue
» MSHR = “Miss Status/Handler Registers” (Kroft)
Each entry in this queue keeps track of status of outstanding
memory requests to one complete memory line.
• Per cache-line: keep info about memory address.
• For each word: register (if any) that is waiting for result.
• Used to “merge” multiple requests to one memory line
» New load creates MSHR entry and sets destination register to
“Empty”. Load is “released” from pipeline.
» Attempt to use register before result returns causes
instruction to block in decode stage.
» Limited “out-of-order” execution with respect to loads.
Popular with in-order superscalar architectures.
• Out-of-order pipelines already have this functionality
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built in… (load queues, etc).
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Lec 15.12
Review: Cache Performance
CPU time = (CPU execution clock cycles +
Memory stall clock cycles) x clock cycle time
Memory stall clock cycles =
(Reads x Read miss rate x Read miss penalty +
Writes x Write miss rate x Write miss penalty)
Memory stall clock cycles =
Memory accesses x Miss rate x Miss penalty
Average Memory Access time (AMAT) =
Hit Time + (Miss Rate x Miss Penalty)
Note: memory hit time is included in execution cycles.
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Lec 15.13
Impact on Performance
• Suppose a processor executes at
– Clock Rate = 200 MHz (5 ns per cycle), Ideal (no misses) CPI = 1.1
– 50% arith/logic, 30% ld/st, 20% control
• Suppose that 10% of memory operations get 50 cycle
miss penalty
• Suppose that 1% of instructions get same miss penalty
• CPI = ideal CPI + average stalls per instruction
1.1(cycles/ins) +
[ 0.30 (DataMops/ins)
x 0.10 (miss/DataMop) x 50 (cycle/miss)] +
[ 1 (InstMop/ins)
x 0.01 (miss/InstMop) x 50 (cycle/miss)]
= (1.1 + 1.5 + .5) cycle/ins = 3.1
• 58% of the time the proc is stalled waiting for memory!
• AMAT=(1/1.3)x[1+0.01x50]+(0.3/1.3)x[1+0.1x50]=2.54
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Lec 15.14
Review: Four Questions for
Memory Hierarchy Designers
• Q1: Where can a block be placed in the upper level?
(Block placement)
– Fully Associative, Set Associative, Direct Mapped
• Q2: How is a block found if it is in the upper level?
(Block identification)
– Tag/Block
• Q3: Which block should be replaced on a miss?
(Block replacement)
– Random, LRU
• Q4: What happens on a write?
(Write strategy)
– Write Back or Write Through (with Write Buffer)
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Lec 15.15
Review: Improving Cache
Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.
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Lec 15.16
Reducing Misses
• Classifying Misses: 3 Cs
– Compulsory—The first access
to a block is not in the cache,
so the block must be brought into the cache. Also called cold
start misses or first reference misses.
(Misses in even an Infinite Cache)
– Capacity—If
the cache cannot contain all the blocks needed
during execution of a program, capacity misses will occur due to
blocks being discarded and later retrieved.
(Misses in Fully Associative Size X Cache)
– Conflict—If
block-placement strategy is set associative or
direct mapped, conflict misses (in addition to compulsory &
capacity misses) will occur because a block can be discarded and
later retrieved if too many blocks map to its set. Also called
collision misses or interference misses.
(Misses in N-way Associative, Size X Cache)
• More recent, 4th “C”:
– Coherence - Misses caused
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by cache coherence.
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Lec 15.17
3Cs Absolute Miss Rate
(SPEC92)
0.14
1-way
Conflict
Miss Rate per Type
0.12
2-way
0.1
4-way
0.08
8-way
0.06
Capacity
0.04
0.02
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64
32
16
8
Cache Size (KB)
128
Compulsory vanishingly
small
4
2
1
0
Compulsory
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Lec 15.18
2:1 Cache Rule
miss rate 1-way associative cache size X
= miss rate 2-way associative cache size X/2
0.14
1-way
Conflict
Miss Rate per Type
0.12
2-way
0.1
4-way
0.08
8-way
0.06
Capacity
0.04
0.02
Cache Size (KB)
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128
64
32
16
8
4
2
1
0
Compulsory
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Lec 15.19
3Cs Relative Miss Rate
100%
Miss Rate per Type
1-way
80%
Conflict
2-way
4-way
8-way
60%
40%
Capacity
20%
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128
64
Flaws: for fixed block size
Good: insight => invention Cache Size (KB)
32
16
8
4
2
1
0%
Compulsory
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Lec 15.20
How Can Reduce Misses?
• 3 Cs: Compulsory, Capacity, Conflict
• In all cases, assume total cache size not changed:
• What happens if:
1) Change Block Size:
Which of 3Cs is obviously affected?
2) Change Associativity:
Which of 3Cs is obviously affected?
3) Change Compiler:
Which of 3Cs is obviously affected?
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Lec 15.21
1. Reduce Misses via Larger
Block Size
25%
1K
20%
Miss
Rate
4K
15%
16K
10%
64K
5%
256K
256
128
64
32
16
0%
Block Size (bytes)
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Lec 15.22
2. Reduce Misses via Higher
Associativity
• 2:1 Cache Rule:
– Miss Rate DM cache size N Miss Rate 2-way cache
size N/2
• Beware: Execution time is only final measure!
– Will Clock Cycle time increase?
– Hill [1988] suggested hit time for 2-way vs. 1-way
external cache +10%,
internal + 2%
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Lec 15.23
Example: Avg. Memory Access
Time vs. Miss Rate
• Example: assume CCT = 1.10 for 2-way, 1.12 for
4-way, 1.14 for 8-way vs. CCT direct mapped
Cache Size
(KB)
1
2.33
2
1.98
4
1.72
8
1.46
16
1.29
32
1.20
64
1.14
128
1.10
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Associativity
1-way 2-way
2.15
2.07
1.86
1.76
1.67
1.61
1.48
1.47
1.32
1.32
1.24
1.25
1.20
1.21
1.17
1.18
4-way 8-way
2.01
1.68
1.53
1.43
1.32
1.27
1.23
1.20
(Red means A.M.A.T. not improved by more associativity)
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Lec 15.24
3. Reducing Misses via a
“Victim Cache”
• How to combine fast hit
time of direct mapped
yet still avoid conflict
misses?
• Add buffer to place data
discarded from cache
• Jouppi [1990]: 4-entry
victim cache removed
20% to 95% of conflicts
for a 4 KB direct mapped
data cache
• Used in Alpha, HP
machines
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TAGS
DATA
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
To Next Lower Level In
Hierarchy
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Lec 15.25
4. Reducing Misses via
“Pseudo-Associativity”
• How to combine fast hit time of Direct Mapped and
have the lower conflict misses of 2-way SA cache?
• Divide cache: on a miss, check other half of cache to
see if there, if so have a pseudo-hit (slow hit)
Hit Time
Pseudo Hit Time
Miss Penalty
Time
• Drawback: CPU pipeline is hard if hit takes 1 or 2
cycles
– Better for caches not tied directly to processor (L2)
– Used in MIPS R1000 L2 cache, similar in UltraSPARC
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Lec 15.26
CS 252 Administrivia
• Still don’t have test graded (Really sorry!)
– I had a date at the WhiteHouse….
• Upcoming events in CS 252
– 27-Oct Final project Proposal due (Friday)
Submission as link from project-specific web page. Due by 5:00.
– I will read-over and respond to people’s email tonight.
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Lec 15.27
5. Reducing Misses by Hardware
Prefetching of Instructions & Datals
• E.g., Instruction Prefetching
– Alpha 21064 fetches 2 blocks on a miss
– Extra block placed in “stream buffer”
– On miss check stream buffer
• Works with data blocks too:
– Jouppi [1990] 1 data stream buffer got 25% misses from
4KB cache; 4 streams got 43%
– Palacharla & Kessler [1994] for scientific programs for 8
streams got 50% to 70% of misses from
2 64KB, 4-way set associative caches
• Prefetching relies on having extra memory
bandwidth that can be used without penalty
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Lec 15.28
6. Reducing Misses by
Software Prefetching Data
• Data Prefetch
– Load data into register (HP PA-RISC loads)
– Cache Prefetch: load into cache
(MIPS IV, PowerPC, SPARC v. 9)
– Special prefetching instructions cannot cause faults;
a form of speculative execution
• Issuing Prefetch Instructions takes time
– Is cost of prefetch issues < savings in reduced misses?
– Higher superscalar reduces difficulty of issue bandwidth
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Lec 15.29
7. Reducing Misses by
Compiler Optimizations
• McFarling [1989] reduced caches misses by 75%
on 8KB direct mapped cache, 4 byte blocks in
software
• Instructions
– Reorder procedures in memory so as to reduce conflict misses
– Profiling to look at conflicts(using tools they developed)
• Data
– Merging Arrays: improve spatial locality by single array of compound
elements vs. 2 arrays
– Loop Interchange: change nesting of loops to access data in order
stored in memory
– Loop Fusion: Combine 2 independent loops that have same looping and
some variables overlap
– Blocking: Improve temporal locality by accessing “blocks” of data
repeatedly vs. going down whole columns or rows
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Lec 15.30
Merging Arrays Example
/* Before: 2 sequential arrays */
int val[SIZE];
int key[SIZE];
/* After: 1 array of stuctures */
struct merge {
int val;
int key;
};
struct merge merged_array[SIZE];
Reducing conflicts between val & key;
improve spatial locality
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Lec 15.31
Loop Interchange Example
/* Before */
for (k = 0; k < 100; k = k+1)
for (j = 0; j < 100; j = j+1)
for (i = 0; i < 5000; i = i+1)
x[i][j] = 2 * x[i][j];
/* After */
for (k = 0; k < 100; k = k+1)
for (i = 0; i < 5000; i = i+1)
for (j = 0; j < 100; j = j+1)
x[i][j] = 2 * x[i][j];
Sequential accesses instead of striding
through memory every 100 words; improved
spatial locality
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Lec 15.32
Loop Fusion Example
/* Before */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
a[i][j] = 1/b[i][j] * c[i][j];
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
d[i][j] = a[i][j] + c[i][j];
/* After */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
{
a[i][j] = 1/b[i][j] * c[i][j];
d[i][j] = a[i][j] + c[i][j];}
2 misses per access to a & c vs. one miss per
access; improve spatial locality
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Lec 15.33
Blocking Example
/* Before */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
{r = 0;
for (k = 0; k < N; k = k+1){
r = r + y[i][k]*z[k][j];};
x[i][j] = r;
};
• Two Inner Loops:
– Read all NxN elements of z[]
– Read N elements of 1 row of y[] repeatedly
– Write N elements of 1 row of x[]
• Capacity Misses a function of N & Cache Size:
– 2N3 + N2 => (assuming no conflict; otherwise …)
• Idea: compute on BxB submatrix that fits
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Lec 15.34
Blocking Example
/* After */
for (jj = 0; jj < N; jj = jj+B)
for (kk = 0; kk < N; kk = kk+B)
for (i = 0; i < N; i = i+1)
for (j = jj; j < min(jj+B-1,N); j = j+1)
{r = 0;
for (k = kk; k < min(kk+B-1,N); k = k+1) {
r = r + y[i][k]*z[k][j];};
x[i][j] = x[i][j] + r;
};
• B called Blocking Factor
• Capacity Misses from 2N3 + N2 to 2N3/B +N2
• Conflict Misses Too?
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Lec 15.35
Reducing Conflict Misses by Blocking
Miss Rate
0.1
Direct Mapped Cache
0.05
Fully Associative Cache
0
0
50
100
150
Blocking Factor
• Conflict misses in caches not FA vs. Blocking size
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– Lam et al [1991] a blocking factor of 24 had a fifth the misses
vs. 48 despite both fit in cache
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Lec 15.36
Summary of Compiler Optimizations to
Reduce Cache Misses (by hand)
vpenta (nasa7)
gmty (nasa7)
tomcatv
btrix (nasa7)
mxm (nasa7)
spice
cholesky
(nasa7)
compress
1
1.5
2
2.5
3
Performance Improvement
merged
arrays
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loop
interchange
loop fusion
blocking
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Lec 15.37
Summary

CPUtime  IC  CPI

E xecutio n

Memory accesses

 Miss rate Miss penalty  Clock cycle time

Instruction
• 3 Cs: Compulsory, Capacity, Conflict
1.
2.
3.
4.
5.
6.
7.
Reduce Misses via Larger Block Size
Reduce Misses via Higher Associativity
Reducing Misses via Victim Cache
Reducing Misses via Pseudo-Associativity
Reducing Misses by HW Prefetching Instr, Data
Reducing Misses by SW Prefetching Data
Reducing Misses by Compiler Optimizations
• Remember danger of concentrating on just one
parameter when evaluating performance
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Lec 15.38
Review: Improving Cache
Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.
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Lec 15.39
1. Reducing Miss Penalty:
Read Priority over Write on Miss
• Write through with write buffers offer RAW
conflicts with main memory reads on cache misses
• If simply wait for write buffer to empty, might
increase read miss penalty (old MIPS 1000 by
50% )
• Check write buffer contents before read;
if no conflicts, let the memory access continue
• Write Back?
– Read miss replacing dirty block
– Normal: Write dirty block to memory, and then do the read
– Instead copy the dirty block to a write buffer, then do the
read, and then do the write
– CPU stall less since restarts as soon as do read
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Lec 15.40
2. Reduce Miss Penalty:
Subblock Placement
• Don’t have to load full block on a miss
• Have valid bits per subblock to indicate
valid
• (Originally invented to reduce tag storage)
Valid Bits
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Subblocks
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Lec 15.41
3. Reduce Miss Penalty:
Early Restart and Critical Word
First
• Don’t wait for full block to be loaded before
restarting CPU
– Early restart—As soon as the requested word of the block
ar rives, send it to the CPU and let the CPU continue execution
– Critical Word First—Request the missed word first from memory
and send it to the CPU as soon as it arrives; let the CPU continue
execution while filling the rest of the words in the block. Also
called wrapped fetch and requested word first
• Generally useful only in large blocks,
• Spatial locality a problem; tend to want next
sequential word, so not clear if benefit by early
restart
block
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Lec 15.42
4. Reduce Miss Penalty: Nonblocking Caches to reduce stalls on
misses
• Non-blocking cache or lockup-free cache allow data
cache to continue to supply cache hits during a miss
– requires F/E bits on registers or out-of-order execution
– requires multi-bank memories
• “hit under miss” reduces the effective miss penalty
by working during miss vs. ignoring CPU requests
• “hit under multiple miss” or “miss under miss” may
further lower the effective miss penalty by
overlapping multiple misses
– Significantly increases the complexity of the cache controller as
there can be multiple outstanding memory accesses
– Requires muliple memory banks (otherwise cannot support)
– Penium Pro allows 4 outstanding memory misses
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Lec 15.43
Value of Hit Under Miss for SPEC
Hit Under i Misses
2
1.8
Avg. Mem. Acce ss Time
1.6
1.4
0->1
1.2
1->2
1
2->64
0.8
B as e
0.6
0.4
0->1
1->2
2->64
Base
“Hit under n Misses”
0.2
Integer
ora
spice2g6
nasa7
alvinn
hydro2d
mdljdp2
wave5
su2cor
doduc
swm256
tomcatv
fpppp
ear
mdljsp2
compress
xlisp
espresso
eqntott
0
Floating Point
• FP programs on average: AMAT= 0.68 -> 0.52 -> 0.34 -> 0.26
• Int programs on average: AMAT= 0.24 -> 0.20 -> 0.19 -> 0.19
• 8 KB Data Cache, Direct Mapped, 32B block, 16 cycle missCS252/Kubiatowicz
10/25/00
Lec 15.44
5th Miss Penalty
• L2 Equations
AMAT = Hit TimeL1 + Miss RateL1 x Miss PenaltyL1
Miss PenaltyL1 = Hit TimeL2 + Miss RateL2 x Miss PenaltyL2
AMAT = Hit TimeL1 +
Miss RateL1 x (Hit TimeL2 + Miss RateL2 + Miss PenaltyL2)
• Definitions:
– Local miss rate— misses in this cache divided by the total number of
memory accesses to this cache (Miss rateL2)
– Global miss rate—misses in this cache divided by the total number of
memory accesses generated by the CPU
(Miss RateL1 x Miss RateL2)
– Global Miss Rate is what matters
10/25/00
CS252/Kubiatowicz
Lec 15.45
Comparing Local and Global
Miss Rates
• 32 KByte 1st level cache;
Increasing 2nd level cache
• Global miss rate close to
single level cache rate
provided L2 >> L1
• Don’t use local miss rate
• L2 not tied to CPU clock
cycle!
• Cost & A.M.A.T.
• Generally Fast Hit Times
and fewer misses
• Since hits are few, target
miss reduction
10/25/00
Linear
Cache Size
Log
Cache Size
CS252/Kubiatowicz
Lec 15.46
Reducing Misses:
Which apply to L2 Cache?
• Reducing Miss Rate
1.
2.
3.
4.
5.
6.
7.
10/25/00
Reduce Misses via Larger Block Size
Reduce Conflict Misses via Higher Associativity
Reducing Conflict Misses via Victim Cache
Reducing Conflict Misses via Pseudo-Associativity
Reducing Misses by HW Prefetching Instr, Data
Reducing Misses by SW Prefetching Data
Reducing Capacity/Conf. Misses by Compiler Optimizations
CS252/Kubiatowicz
Lec 15.47
L2 cache block size &
A.M.A.T.
Relative CPU Time
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.95
1.54
1.36
16
1.28
1.27
32
64
1.34
128
256
512
Block Size
• 32KB L1, 8 byte path to memory
10/25/00
CS252/Kubiatowicz
Lec 15.48
Reducing Miss Penalty Summary

CPUtime  IC  CPI

E xecutio n

Memory accesses

 Miss rate Miss penalty  Clock cycle time

Instruction
• Five techniques
–
–
–
–
–
Read priority over write on miss
Subblock placement
Early Restart and Critical Word First on miss
Non-blocking Caches (Hit under Miss, Miss under Miss)
Second Level Cache
• Can be applied recursively to Multilevel Caches
– Danger is that time to DRAM will grow with multiple levels in
between
– First attempts at L2 caches can make things worse, since
increased worst case is worse
10/25/00
CS252/Kubiatowicz
Lec 15.49
What is the Impact of What
You’ve Learned About Caches?
1000
10/25/00
2000
1999
1998
DRA M
1997
1996
1995
1994
1993
1992
1991
1990
1989
1988
1987
1986
1985
1984
1983
1982
1981
1980
• 1960-1985: Speed
= ƒ(no. operations)
• 1990
100
– Pipelined
Execution &
Fast Clock Rate
10
– Out-of-Order
execution
– Superscalar
Instruction Issue 1
• 1998: Speed =
ƒ(non-cached memory accesses)
• Superscalar, Out-of-Order machines hide L1 data cache miss
(5 clocks) but not L2 cache miss (50 clocks)?
CPU
CS252/Kubiatowicz
Lec 15.50
Cache Optimization Summary
miss penalty
miss rate
Technique
10/25/00
Larger Block Size
Higher Associativity
Victim Caches
Pseudo-Associative Caches
HW Prefetching of Instr/Data
Compiler Controlled Prefetching
Compiler Reduce Misses
Priority to Read Misses
Subblock Placement
Early Restart & Critical Word 1st
Non-Blocking Caches
Second Level Caches
MR
+
+
+
+
+
+
+
MP HT
–
+
+
+
+
+
–
+
Complexity
0
1
2
2
2
3
0
1
1
2
3
2
CS252/Kubiatowicz
Lec 15.51