Transcript BEE3 Updates June 13th, 2007 Chuck Thacker, John Davis Microsoft Research Chen Chang UC Berkeley.

BEE3 Updates
June 13th, 2007
Chuck Thacker, John Davis
Microsoft Research
Chen Chang
UC Berkeley
BEE3 Overview
305.00
4 Xilinx FPGA: (FF1136)
RJ45
35.00
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM
12V
4-pin
21.00
1.8V
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM
1.8V
1.8V
1.0V
1.0V
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM
QSH-DP-040
QSH-DP-040
5VLXT
FF1136
QSH-DP-040
40.00
70.00
180.00
10.00
23.00
18.00
102.00
29.00
24 pin ATX PWR
150.00
1.8V
12V
8-pin
2.5V
5VLXT
FF1136
78.00
65.00
50 pin 2mm Header
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM
JTAG
PCI-Express 8x
PCI-Express 8x
380.00
QSH-DP-040

100.00
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM
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8 10GBase-CX4 interfaces
4 PCI-E x8 slots (endpoints)
4 QSH-DP (40 LVDS pairs)
daughter card & cable
connectors
4 GE RJ45 interfaces
2U chassis
ATX12V/EPS2U 500W power
supply
5VLXT
FF1136
PCI-Express 8x
60.00
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM

PCI-Express 8x
16 DIMMs
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM

30.00
Fujitsu 2x2
CX4
40.00
4 GB DDR2-667 DRAM
4 GB DDR2-667 DRAM

15.00
20.00
◦ 2 DDR2-400/533/667
channels per FPGA
◦ Up to two 4GB DIMMs per
channel

25.00
Fujitsu 2x2
CX4
RJ45
◦ Virtex-5 LX110T or SX95T

105.00
5VLXT
FF1136

105.00
25.00
107.00
180.00
BEE3 Package
June 2007 RAMP Tutorial
BEE3 Package Front View
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Control I/O Panel:
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4 RS232(RJ45)
4 SD card slots
1 CF card (SystemACE)
1 Xilinx USB-JTAG
2 SMA clock input
1 Power reset
1 FPGA soft reset
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Data I/Os:
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◦
◦
◦
◦
4 PCIe slots
8 CX4 connectors
4 RJ45
4 FPGA done LEDs
4 FPGA user LEDs
June 2007 RAMP Tutorial
FPGA I/O Interfaces
COTS PCI-Express over Cable
Solution from One Stop Systems
HIB2 x8 Host
PCIe x8 cable
Up to 7 meters
HIB2 x8 Target
Peak I/O Bandwidths (per-FPGA)
(estimates for XC5VLX110T-1 part)

DDR2 Memory
◦ 400 MT/s * 8B/T * 2 channels: 6.4 GB/s

Ring
◦ 400 MT/s * 8 B/T * 2 channels: 6.4 GB/s

QSH
◦ 400 MT/s * 4 B/T: 1.6 GB/s

Ethernet
◦ 125 MB/s

CX4
◦ 1.25 GB/s * full duplex * 2 channels: 5GB/s

PCI Express x8
◦ 2GB/s * full duplex: 4GB/s
June 2007 RAMP Tutorial
Schedule
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Generate Specification – Done
Schematic Entry – Done
Board Layout – Started
Thermal modeling, heat sink design – Started
Chassis design -- Started
Signal Integrity – Imminent
Prototypes: Late Summer – Bring-up starts
Production: Start early 2008
June 2007 RAMP Tutorial