A 2-GHz Direct Sampling ΔΣ Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL T. Chalvatzis 1 , T. O. Dickson 1,2 and S. P. Voinigescu 1

1 University of Toronto, Toronto, CA 2 now with IBM T.J. Watson Research Center, NY, USA

Outline of Presentation

• • • •

Motivation Circuit design

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Loop filter

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PLL Measurement results Summary

Motivation

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Direct sampling receiver for 2-GHz radio with 60 MHz BW

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CT BP ΔΣ ADC with SNDR of 55dB/60MHz [Chalvatzis et al., JSSC, May 2007]

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Investigation of clock jitter impact with on-chip clock source Digital Receiver LNA TO DSP ADC Duplexer/BPF CLOCK

System Architecture

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2-GHz Gm-LC BPF RF Fourth order loop 1-bit quantizer as DFF INPUT with F CLK =40GHz RZ pulse DACs G m1 LNA 2GHz BPF RZ DAC1 G fb1 G m2 2GHz BPF DFF D Q G fb2 RZ DAC2 40-GHz VCO/PLL 2.5-GHz REF PFD CP 40-GHz VCO CLOCK SELECT CLOCK TREE DIV/16 SEL 40-GHz EXTERNAL CLOCK DRIVER DIGITAL OUTPUT

System Level Design

• • •

Design methodology in continuous-time System level simulation for accurate analysis of loop delay Loop coefficients:

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Gm1=22mS, Gm2=15mS

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Gfb1=50mS, Gfb2=150mS SNDR=61dB over 60 MHz in Matlab Simulink

SNR vs clock jitter

SNR= 2 V IN 2 2OSR  F 2 DAC σ t 2

Δ: quantizer step [Ortmanns et al., ISCAS 2003]

• •

Clock jitter effect simulated for F S =40GHz, OSR=333 PLL jitter < 1.4 ps (rms) for 10 bits resolution

SNR vs resonator Q

• •

Quantization noise integrated over BW for F S =40GHz Q >18 for 10 bits resolution

SNR=  2 6

F S



F O F O

 

BW BW

/ 2 / 2 2 V IN )

Loop Filter

• •

MOS-HBT cascode for high linearity and low noise EF limit voltage headroom, current source adds noise

Loop filter with EF

BPF C C C VAR L C V CC (2.5V) BPF C C C VAR L C V B Q1 V TUNE Q2 V B OUTP Q5 V B Q3 V TUNE Q4 OUTN V B INP M1 M2 INN M3 L E LNA/Gm1 L E L EE,1 VGTAIL M5 Gm2 M4 M6 M7

Modified Loop Filter

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MOS-HBT cascode for high linearity and low noise EF limit voltage headroom, current source adds noise

Modified Loop Filter

BPF C C C VAR L C V CC (2.5V) BPF C C C VAR L C INP V B Q1 V TUNE Q2 M1 M2 C B OUTP V B C B INN V B Q3 V TUNE Q4 M3 M4 OUTN V B L E LNA/Gm1 L EE,1 L E V G R G Gm2 L EE,2 R G

DFFP D/A Converter – Quantizer V CC (2.5V) DACP DACN V CC (2.5V) Q3 Q4 V B Q1 Q2 DFFN INP INN CLKN CLKP CLKP M1 M2 OUTP CLKN OUTN VGTAIL M3 I TAIL V G

DAC Latch • • •

DAC and quantizer with MOS-HBT cascodes [Chalvatzis et al., JSSC, May 2007] MOS on clock path to improve speed with low supply HBT on data path for high gain

Digital Receiver – PLL Blocks V CC (2.5V) R L '1' REF Phase Frequency Detector UP D Q RESET '1' DIV D Q DOW N Charge Pum p To Loop Filter D CLK R L Q1 Q2 M 1 R L Q3 Q4 M 2 Q5 Q6 M 3 R L Q7 Q M 4 RESET V BIAS

Resettable Latch • •

40-GHz PLL design from 2.5V challenging Combination of MOS-HBT transistors in PLL blocks

Digital Receiver – PLL Blocks V CC (2.5V) '1' REF Phase Frequency Detector UP D Q RESET '1' DIV D Q DOW N Charge Pum p To Loop Filter UP I REF DOW N CM FB V TUNE

Charge Pump • •

40-GHz PLL design from 2.5V challenging Combination of MOS-HBT transistors in PLL blocks

VCO V CC (2.5V) L P Q1 C N L B C 1 C VARN V BIAS V TUNEN L L B C N Q2 C 1 C VARN P

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Colpitts VCO topology with HBT [Dickson et al., CSICS 2006] VCO biased for minimum phase noise Differential tuning with accumulation mode MOS varactors C VARP V TUNEP C VARP L EE C CM R CM L EE

Fabrication and characterization of digital receiver

Fabrication ADC DIGITAL OUT RF IN PLL REF

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ADC with on chip VCO/PLL in STM 0.13

μm SiGe BiCMOS Power dissipation 2.19W from 2.5V

Chip size 1.59x2.39mm

2 PLL SEL

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PLL measurements Phase noise/jitter measured on PLL test structure RMS jitter: σ t =849fs Jitter limited SNR for F o =2GHz and OSR=333 -> SNR=66.7dB

VCO measurements

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Phase noise < -103dBc/Hz at 1 MHz offset from 40-GHz carrier

Spectrum measurement with PLL

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ADC tested with external and on-chip clock No significant degradation from on-chip clock Feedthrough from 2.5GHz PLL reference does not degrade performance

SFDR measurement SFDR=59dB

SNDR measurement SNDR measured for F IN =2GHz, FS=40GHz SNDR = 59.8dB over 60 MHz

Dynamic Range ADC noise floor the same (-65dBm/60MHz) when external and on-chip clock employed

Digital Receiver Performance Fo Fs BW SNDR ENOB SFDR P 1dB DR Power FoM 2GHz 40GHz 60MHz 59.8dB

9.65bits

59dB -2.8dBm

58.5dB

2.19W

65.5GHz/W 15.3pJ/bit

FoM= 2 ENOB ×2BW P DC

Conclusion

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First mm-wave sampling ΔΣ digital receiver in any semiconductor technology Digital receiver achieves 9.65-bit resolution over 60 MHz Removing EF pair in filter helps to increase linearity of ADC loop filter For 10-bits resolution, jitter from on-chip VCO/PLL not limiting performance Noise floor set by resonator Q

Acknowledgements

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Nortel Networks for funding support John Ilowski and Eric Gagnon for discussions STMicroelectronics for chip fabrication Prof Miles Copeland for advice on the manuscript Ricardo Aroca for help with testing CMC for CAD tools Jaro Pristrupa for CAD support