Transcript Lecture 6 Multioperand Addition Modular Addition Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 8, Multioperand Addition Chapter 7.6, Modular Two-Operand Adders.

Lecture 6
Multioperand Addition
Modular Addition
Required Reading
Behrooz Parhami,
Computer Arithmetic: Algorithms and Hardware Design
Chapter 8, Multioperand Addition
Chapter 7.6, Modular Two-Operand Adders
Applications of multioperand addition
Inner product
Multiplication
p=a·x
s=
n-1
n-1
i=0
i=0
 x(i) y(i) =  p(i)
Number of bits of the result
n-1
S=
 x(i)
x(i) [0..2k-1]
i=0
Smin = 0
Smax = n (2k-1)
# of bits of S = log2 (Smax + 1)
= log2 (n (2k-1) + 1) 
= k + log2 n
=
log2 n 2k =
Serial implementation of multioperand addition
Adding 7 numbers in the binary tree of adders
Ripple-carry adders at levels i and i+1
Example: Adding 8 3-bit numbers
Ripple-Carry Carry Propagate Adder (CPA)
a2 b2
ak-1 bk-1
ck
FA
sk-1
ck-1
...
c3
FA
s2
a1 b1
c2
FA
s1
a0 b0
c1
FA
s0
c0
Carry Save Adder (CSA)
ak-1 bk-1 ck-1
ck
a2 b2 c2
a1 b1 c1
a0 b0 c0
FA
...
FA
FA
FA
sk-1 ck-1
s3 c3
s2 c2
s1 c1
s0
A Ripple-Carry vs. Carry-Save Adder
Operation of a Carry Save Adder (CSA)
Example
24 23 22 21 20
x
y
z
0 1 0 1 0
1 1 0 1 1
1 0 1 1 1
0 0 1 1 0
s
c 1 1 0 1 1
x+y+z = s + c
Carry propagate and carry-save adders
in dot notation
cin
Carry-propagate adder
cout
Carry-save adder (CSA)
or
(3; 2)-counter
or
3-to-2 reduction circuit
Specifying full- and half-adder blocks
in dot notation
Full-adder
Half-adder
Carry-save adder for four operands
x3 x 2 x1 x0
y3 y 2 y1 y0
z3 z 2 z1 z0
w3 w2 w1 w0
s3 s 2 s1 s0
c4 c3 c 2 c1
w3 w2 w1 w0
c4 s’3 s’2 s’1 s’0
c4’ c’3 c’2 c’1
S5 S4 S3 S2 S1 S0
Carry-save adder for four operands
c4
c4’
s3
c3
s2
c2
s3’
c3’
s2’
c’2
s1
s’1
c1
c1’
s0
s’0
Carry-save adder for four operands
z
y
x
w
CSA
c
s
CSA
s’
c’
CPA
S
Carry-save adder for six operands
CSA tree
Implementation of
one-bit slice
Tree of carry save adders reducing
seven numbers to two
12 FAs
Addition of seven
six-bit numbers
in dot notation
6 FAs
6 FAs
4 FAs + 1 HA
7-bit adder
Total cost = 7-bit adder + 28 FAs + 1 HA
[0 , k –1 ]
[0 , k –1 ]
[0 , k –1 ]
[0 , k –1 ]
k -bit CSA
[1 , k ]
[0 , k –1 ]
[0 , k –1 ]
[0 , k –1 ]
k -bit CSA
[0 , k –1 ]
[0 , k –1 ]
[1 , k ]
k -bit CSA
Adding seven
k-bit numbers:
block diagram
[1 , k ]
[0 , k –1 ]
k -bit CSA
[2 , k +1 ]
The ind ex pair
[i , j] mean s t hat
b it p os iti on s
from i u p to j
are i nv olv ed .
[1 , k –1 ]
[1 , k ]
k -bit CSA
[1 , k +1 ]
[2 , k +1 ]
[2 , k +1 ]
k -bit CP A
k +2
[2 , k +1 ]
1
0
Relationship Between
Number of Inputs and Tree Height
n inputs
. . .
h levels
h levels
2 outputs
Parameters of tree carry-save adders (1)
Latency
LatencyCSA =
h(n)  TFA + LatencyCPA(k, n)
Tree height
for n operands
Component Adders
Widths
CSA
k .. k + log2 n
CPA
 k + log2 n
typically
close to k bits
Parameters of tree carry-save adders (2)
Maximum number of inputs that can be reduced
to two by an h-level tree, n(h)
n(0) = 2
3
n(h) =
n(h-1)
2
n(1) = 3
n(2) = 4
n(3) = 6
n(4) = 9
n(5) = 13
n(6) = 19
2
3 h-1
< n(h)  2
2
( )
3 h
2
( )
Parameters of tree carry-save adders (3)
Smallest height of the tree carry save adder
for n operands, h(n)
h(n) = 1 + h
2
n
3
(
)
h(2) = 0
h(n)  log 3
2
n
2
( )
Wallace vs. Dadda Trees (1)
Wallace trees
• Reduce the size of the final Carry Propagate Adder (CPA)
• Optimum from the point of view of speed
Dadda trees
• Reduce the cost of the carry save tree
• Optimum (among the CSA trees) from the point of
view of area
Wallace vs. Dadda Trees (2)
• Wallace reduces number of operands at earliest
opportunity
– Goal of this is to have smallest number of bits
for CPA adder
– However, sometimes having a few bits longer
CPA adder does not affect the propagation
delay significantly (i.e. carry-lookahead)
• Dadda seeks to reduce the number of FA and HA
units
– May be at the cost of a slightly larger final CPA
5-to-3 Parallel Counter
24 23 22 21 20
a
b
c
d
e
0
1
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0 1 1 1 0
s0
0 1 1 0 0
s1
s2 1 0 0 1 1
a+b+c+d+e = s0+s1+s2
Implementation of 1-bit of 5-to-3 parallel counter
using single CLB slice of a Virtex FPGA
S2
d
c
b
LUT G
‘0’
a
d
c
b
S1
LUT F
S0
a
e
Carry Save Adder vs. 5-to-3 Parallel Counter
a
w
b
c
d e
w w
w
w
a
w
c
b
w
CSA
w
d
w
e
w
PC
s2
CSA
s1
s0
CSA
CSA
CPA
CPA
w
w
y=a+b+c+d+e mod 2w
y=a+b+c+d+e mod 2w
Generalized Parallel Counters
Multicolumn
reduction
(5, 5; 4)-counter
Unequal
columns
.
.
.
Fig. 8.17 Dot notation for a (5, 5; 4)-counter
and the use of such counters for reducing five
numbers to two numbers.
Generalized parallel counter =
Parallel compressor
(2, 3; 3)-counter
Related Question from
the Last Year’s Exam
Pseudocode
sum = 0
for i = 0 to 3 do
sum = sum + A + B + C + D
end for
average = sum / 24
clk
8
8
Z
A
B
C
D
4
4
4
4
S
8
Reg
>>4
sum
A
B
C
D
4
average
MADD
reset
Design and analyze the multi-operand adder MADD
shown above by
a. Drawing the dot diagram of the operations performed by
MADD.
b. Drawing a block diagram of MADD
using medium level components, such as full-adders
and half-adders.