Transcript Automated FSM Error Correction for Single Event Upsets Dr. Nand Kumar & Darren Zacher Design Creation and Synthesis Division Mentor Graphics Corp. 2004 MAPLD Int’l.

Automated FSM Error Correction
for Single Event Upsets
Dr. Nand Kumar & Darren Zacher
Design Creation and Synthesis Division
Mentor Graphics Corp.
2004 MAPLD Int’l Conference – Paper 118
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Kumar
Introduction/Agenda

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Challenges
Proposal
Methodology
Results
Discussion
Lessons Learned
Conclusions
2004 MAPLD Int’l Conference – Paper 118
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Challenges

Harsh operating environments
–
–

Increasing pressures to control costs
–
–

Single Event Upsets (SEUs) are to be expected
Significant design, verification and operational challenges
Accelerated design, verification and deployment cycles
Use of lower-cost parts and smaller device geometries to
accommodate increasing gate count
Dilemma!
2004 MAPLD Int’l Conference – Paper 118
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Proposal (1/4)

Add Hamming error checking bits based on
state encoding
–
–
–
O(log2n) extra storage for parity bits
Parity logic corrects single-bit errors
Can add extra parity bit to detect double-bit errors
2004 MAPLD Int’l Conference – Paper 118
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Proposal (2/4)

Hamming distance increased to three
SH1
S
0
1
00
01
11
10
A
B
2004 MAPLD Int’l Conference – Paper 118
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H2
0
A
A
B
A
1
A
B
B
B
Kumar
Proposal (3/5)
2004 MAPLD Int’l Conference – Paper 118
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Proposal (4/5)
2004 MAPLD Int’l Conference – Paper 118
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Proposal (5/5)

Proposed benefits
–
–
–
–
Fewer extra storage elements required than TMR
Correction in combinatorial logic, less susceptible to
errors, especially in antifuse devices
Can detect double-bit errors with low overhead
Not limited by the FSM encoding
2004 MAPLD Int’l Conference – Paper 118
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Methodology
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Consider several state machines
– Various state encodings
– Various state counts
Compare and contrast error correction
– Hamming encoding of state bits
– Triple Module Redundancy
Target Actel 54SX72A-STD
– Constrain minimally for synthesis and layout
– Prevent register replication
Simulate using bit error injection
– Forced state / hamming parity bits to 0 or 1

Models “persistent SEU”
2004 MAPLD Int’l Conference – Paper 118
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Results (1/7)
Circuit characteristics – Original encodings (TMR)

FSM States
fsm2
fsm1
fsm3
fsm6
fsm7
fsm4
fsm5 6 &
5
6
7
9
23
30
10
Encoding
One-hot
One-hot
Gray
Gray
Gray
Gray
One-hot & Gray
Seq
20
72
238
467
506
427
25
2004 MAPLD Int’l Conference – Paper 118
Normal
Area
Fmax
Area
Comb Agg
Seq Comb
31
51 114.32
30
36
60 132 65.75
82
65
1742 1980 19.87 244 1744
1272 1739 25.12 475 1276
2186 2692 16.35 516 2190
1392 1819 24.33 445 1400
84 109 72.98
57
100
10
TMR
Fmax
Agg
66
147
1988
1751
2706
1845
157
82.72
63.9
19.57
26.99
16.13
24.45
61.33
Chg Area
Seq
Comb
50.0% 16.1%
13.9%
8.3%
2.5%
0.1%
1.7%
0.3%
2.0%
0.2%
4.2%
0.6%
128.0% 19.0%
Chg Fmax
Agg
29.4%
11.4%
0.4%
0.7%
0.5%
1.4%
44.0%
-27.6%
-2.8%
-1.5%
7.4%
-1.3%
0.5%
-16.0%
28.9% 6.4% 12.6%
-5.9%
Kumar
Results (2/7)

Circuit characteristics – Original encodings (Hamming)
FSM States
fsm2
fsm1
fsm3
fsm6
fsm7
fsm4
fsm5 6 &
5
6
7
9
23
30
10
Encoding
One-hot
One-hot
Gray
Gray
Gray
Gray
One-hot & Gray
Seq
20
72
238
467
506
427
25
Normal
Area
Fmax
Area
Comb Agg
Seq Comb
31
51 114.32
23
40
60 132 65.75
75
80
1742 1980 19.87 241 1715
1272 1739 25.12 470 1319
2186 2692 16.35 509 2122
1392 1819 24.33 430 1384
84 109 72.98
32
131
Fmax
Agg
63
155
1956
1789
2631
1814
163
53.46
46.67
18.37
25.61
10.86
18.78
31.46
Hamming
Chg Area
Seq
Comb
15.0%
29.0%
4.2%
33.3%
1.3%
-1.5%
0.6%
3.7%
0.6%
-2.9%
0.7%
-0.6%
28.0%
56.0%
7.2%
2004 MAPLD Int’l Conference – Paper 118
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Chg Fmax
Agg
23.5%
17.4%
-1.2%
2.9%
-2.3%
-0.3%
49.5%
-53.2%
-29.0%
-7.5%
2.0%
-33.6%
-22.8%
-56.9%
16.7% 12.8%
-28.7%
Kumar
Results (3/7)

Circuit characteristics – Original encodings
Sequential Cell Increase
Combinatorial Cell Increase
140%
60%
120%
50%
100%
40%
80%
30%
TMR
60%
TMR
Hamming
20%
Hamming
40%
10%
20%
0%
0%
-10%
Frequency Delta
20%
10%
Seq
TMR
Chg Area
Comb Agg
28.9% 6.4% 12.6%
Chg Fmax
Seq
-5.9% 7.2%
Hamming
Chg Area
Comb
Agg
16.7% 12.8%
Chg Fmax
0%
-10%
-28.7%
TMR
-20%
Hamming
-30%
-40%
-50%
-60%
2004 MAPLD Int’l Conference – Paper 118
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Results (4/7)

Circuit characteristics – Minimal encodings (TMR)
FSM States
Encoding
fsm2
5 Binary
fsm1
6 Binary
fsm3
7 Gray
fsm6
9 Gray
fsm7
23 Gray
fsm4
30 Gray
fsm5 6 & 10 Binary & Gray
Seq
18
70
238
467
506
427
17
Normal
Area
Fmax
Area
Comb Agg
Seq Comb
41
59 112.36
24
44
66
136 59.44
76
69
1742 1980 19.87 244 1744
1272 1739 25.12 475 1276
2186 2692 16.35 516 2190
1392 1819 24.33 445 1400
80
97 70.09
33
88
TMR
Fmax
Agg
68
145
1988
1751
2706
1845
121
94.87
65.9
19.57
26.99
16.13
24.45
65.25
Chg Area
Chg Fmax
Seq Comb Agg
33.3% 7.3% 15.3%
-15.6%
8.6% 4.5% 6.6%
10.9%
2.5% 0.1% 0.4%
-1.5%
1.7% 0.3% 0.7%
7.4%
2.0% 0.2% 0.5%
-1.3%
4.2% 0.6% 1.4%
0.5%
94.1% 10.0% 24.7%
-6.9%
20.9% 3.3% 7.1%
2004 MAPLD Int’l Conference – Paper 118
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-0.9%
Kumar
Results (5/7)

Circuit characteristics – Minimal encodings (Hamming)
FSM States
Encoding
fsm2
5 Binary
fsm1
6 Binary
fsm3
7 Gray
fsm6
9 Gray
fsm7
23 Gray
fsm4
30 Gray
fsm5 6 & 10 Binary & Gray
2004 MAPLD Int’l Conference – Paper 118
Seq
18
70
238
467
506
427
17
Normal
Area
Fmax
Area
Comb Agg
Seq Comb
41
59 112.36
21
43
66
136 59.44
73
74
1742 1980 19.87 241 1715
1272 1739 25.12 470 1319
2186 2692 16.35 509 2122
1392 1819 24.33 430 1384
80
97 70.09
24
79
14
Agg
64
147
1956
1789
2631
1814
103
Hamming
Fmax
Chg Area
Seq Comb
64.96 16.7% 4.9%
58.91 4.3% 12.1%
18.37 1.3% -1.5%
25.61 0.6% 3.7%
10.86 0.6% -2.9%
18.78 0.7% -0.6%
42.46 41.2% -1.3%
Chg Fmax
Agg
8.5%
8.1%
-1.2%
2.9%
-2.3%
-0.3%
6.2%
-42.2%
-0.9%
-7.5%
2.0%
-33.6%
-22.8%
-39.4%
9.3% 2.1% 3.1%
-20.6%
Kumar
Results (6/7)

Circuit characteristics – Minimal encodings
Combinatorial Cell Increase
60%
Sequential Cell Increase
50%
140%
40%
120%
100%
30%
TMR
80%
TMR
60%
Hamming
20%
Hamming
10%
40%
0%
20%
0%
-10%
Frequency Delta
20%
10%
Seq
20.9%
TMR
Chg Area
Comb
Agg
3.3%
7.1%
Chg Fmax
Seq
-0.9%
Hamming
Chg Area
Comb
Agg
9.3%
2.1%
3.1%
Chg Fmax
0%
-10%
-20.6%
TMR
-20%
Hamming
-30%
-40%
-50%
-60%
2004 MAPLD Int’l Conference – Paper 118
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Results (7/7)
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Bit error susceptibility
–
Simulated FSM2 RTL vs. synthesized gates with
1,000 random stimulus patterns
 One state bit forced – No errors
–
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Upset(s) corrected
One parity bit forced – No errors
–
Upset(s) corrected
Two bits forced – Errors found
Initial results encouraging

–
2004 MAPLD Int’l Conference – Paper 118
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Discussion


Hamming encoding more area efficient than
TMR for minimal encodings
Metastability issues?
2004 MAPLD Int’l Conference – Paper 118
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Lessons Learned



Hamming correction overhead comes at a
performance price
Performance penalty larger for one-hot state
encoding
Hamming error recovery will not incur
frequency penalty
2004 MAPLD Int’l Conference – Paper 118
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Conclusions

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
Hamming encoding an acceptable alternative to TMR
Hamming encoding lends itself well to automated
implementation during synthesis
Error susceptibility advantages
– Double-bit errors detectable with Hamming

Scales well with FSM state count

Area penalty half that of TMR for minimal encoding
2004 MAPLD Int’l Conference – Paper 118
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