Transcript A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power in Standard Digital 65nm CMOS Using Dummy-Prefilled Microstrip Lines M.

A 1.1V 150GHz Amplifier with 8dB Gain and
+6dBm Saturated Output Power
in Standard Digital 65nm CMOS
Using Dummy-Prefilled Microstrip Lines
M. Seo1, B. Jagannathan2, C. Carta1, J. Pekarik3,
L. Chen1, C. P. Yue1 and M. Rodwell1
1Dept.
of Electrical and Computer Engineering
University of California, Santa Barbara
2IBM, Burlington, VT
3IBM, Crolles, France
1
Outline
• Introduction
• “Dummy-Prefilled” Microstrip Line
– Structure and Modeling
• Design and Simulation
• Measurement Results
2
Attenuation
Atm. Attenuation
(dB/km) (dB)
Beyond 100GHz: What Applications?
20
15
O2 94GHz
140GHz
H2O
H2O
10
5
0
0
220GHz
O2
50
100
150
200
Frequency
(GHz))
Frequency
(GHz)
250
300
350
• Communication
– Outdoor, indoor
• Imaging (Passive, active)
– Security
– All-weather radar
– Medical
3
Beyond 100GHz: Why CMOS?
• Low-cost
• Low-power
• Large-scale Integration → Parallelism
– Large monolithic phased array, imager.
• RF/mm-wave, IF/analog, DSP on a same die.
– System-on-chip
– Digital calibration of RF/analog circuit imperfections,
process variations.
– Reconfigurability and adaptability
4
What Challenges in 150GHz CMOS Amp?
• Low available FET gain, Low Supply Voltage
– Careful FET layout & sizing
– Multi-stage Common-Source
• Modeling uncertainties
– Simple matching topology with microstrip (MS) lines
• Automatic “dummies” alter MS-line characteristics
– Propose “Dummy-prefilled” MS-line
• Characterization
– Full 2-port on-wafer TRL calibration
5
8
D
S
Parallel
gate feed (PGF)
7
6
5
4
G
3
2
10x1um/65n
D
1
Series
gate feed (SGF)
S
Maximum Stable Gain (dB)
SFG_PFG_MSG_H21_U
G
MSG (PGF)
FET Layout
0
9
100
10
100
200 10
200
9
300
Frequency (GHz)
Frequency (GHz)
G
• Finger design: Reduce Rg,ext and Cgd (WF=1um)
• Wiring multiple fingers: Parallel versus Series
6
“Microstrip Line” in Nanoscale CMOS
Ground plane
• “Automatic” dummies/holes to meet metal density rules.
• Line capacitance increases
– ΔC depends on E-field orientation → Anisotropic
• Direct E/M simulation nearly impossible
7
Possible Shapes of Dummy Pre-fillers
• “LINE” dummies
• Parallel to current flow
dummies
• “LINE” dummies
• Perpendicular to current flow
• “SQUARE” dummies
• No preferred direction of
current flow
8
Reducing Complexity in E/M Sim
Dummy
Pre-fillers
E/M simulation feasible
by significantly reducing
# of dummies
W S
Signal
Signal
Dummy-free uniform dielectric
with adjusted diel. constant
E-field
lines
ε
ε’
Successive dummy-layer substitution
by parallel-plate capacitor simulation
9
Line Inductance/Capacitance vs Fill Ratio
% change
Lul (nH/m)
L per unit length
(317nH/m w/o fillers)
40
20
0
-20
-40
% change
0
10
Cul (pF/m)
20
30
40
Fill Ratio (%)
40
20
0
-20
-40
25% Fill
W:S = 1:1
50
60
+32%
+17%
56% Fill
W:S = 3:1
C per unit length
(103pF/m w/o fillers)
0
10
20
30
40
Fill Ratio (%)
50
60
10
Ground Plane Construction
• Solid GND plane not allowed
• Put holes, and strap M1 & M2
+
M1
M2
via
Where current flow is uniform
(e.g. under MS-line)
Where current flow is not uniform
(e.g. under bends, T-junction,
radial stubs)
11
THRU-REFL-LINE (TRL) Calibration
Half THRU
(1) THRU
450um
(2) REFL
Reference
plane
(Open, short, etc)
ΔL
(3) LINE
(ΔL= 90 deg @center freq)
Amplifier
Test
• REFL & LINE need not be accurately known
• Measurements normalized to the line impedance
12
3-Stage 150GHz Amplifier: Schematic
V2
V3
All TL’s: Z0= 51.2
W=10u
(25% fill)
Radial
stub
TL1
TL2
TL3
TL4
V4
M1
V1
30u/65n
Half THRU
M2
M3
30u/65n
30u/65n
Amplifier
Half THRU
• No DC block: Forces VGS=VDS for M1 & M2, but
eliminates loss and modeling uncertainties associated
with DC-block cap
• FET size is chosen for low matching loss
13
• Radial stub for lower loss than quarter-wave TL
FET Sizing
constant-g
circle (20mS) S22* (g22 g11)
Z0
S11
Large
FET
constant-Q
circle
Small
FET
Conjugate input/output/inter-stage match
with shunt tuning stubs only.
14
Simulated 150-GHz Amplifier Gain
7
S21 (dB)
6
Radial stub
(45deg opening)
AC
short
5
PDC= 25mW
0.65V 1.1V
4
3
¼λ
Open-stub
Z0=34, W=20u
¼λ
Open-stub
Z0=51, W=10u
2
1
0
140
150
160
170
180
190
200
Frequency (GHz)
15
Die Photograph
Dummy-prefilled • Area
radial stub
= 0.4mm2 (w pads)
= 0.16mm2 (w/o pads)
640mm
• Stack: 9 Cu + 1 Al
Dummy-prefilled
MS-lines
Automatic
dummies
Reference
planes
16
640mm
S-parameter Measurement Setup
GGB Probes
W/G
Probe
Station WR05
OML Inc.
140-220GHz
mm-wave heads
Agilent
Coax
8510C
IF/LO VNA
17
Can we trust the calibration?
0.4
S21 (dB)
TRL_THRU_sel(2,2)
TRL_OPEN3(2,2)[i1::i2]
S11THRU < -40dB
0.2
|S21THRU| < 0.1dB
0
-0.2
-0.4
|S11OPEN| < 0.2dB
freq (140.8GHz to 199.3GHz)
S22_sel
S11LINE < -35dB
140 150 160 170 180 190 200
Frequency (GHz)
• Probe coupling < -40dB
• Repeatability issues
– Probe placement
– Probe contact resistance
18
freq (140.5GHz to 199.5GHz)
1mm-long Line
0
|S21| (dB/mm)
|S21| (dB/mm)
Prefilled MS-Line: Measurement
E/M Sim.
-1
-2
-3
-2.0dB/mm
@140GHz
-4
-2.8dB/mm
@200GHz
-5
(deg)
(deg)
Phase
S21Phase
0
20
40
60
0
-20
-40
-60
-80
-100
-120
80 100 120 140
Frequency (GHz)
160
180
200
LINE standard
E/M Sim (8% error)
0
20
40
60
80
100 120 140 160 180 200
Frequency (GHz)
19
Measured Amp. S-Parameters
10
Peak |S21|= 8.2dB
Meas
Sim
S-parameter (dB)
S21
5
PDC= 25.5mW
3dB BW= 27GHz
0.65V
0
-5
1.1V
S11meas
-10
S22
-15
S11sim
-20
140
150
160
170
180
190
200
Frequency (GHz)
20
60
S21 versus
Current Density
10SF 3stg_150ghz
40
0.5~0.9V
V
20
5
0
10
4
3
100
30
6
Pdc [mW]
S21@150GHz
[dB]
S21 (dB)
7
DC Power (mW)
50
8
200 300 400 500 600
Drain Current
Density (uA/um)
Iden [uA/um]
700
21
S21 (dB)
S21 @Higher Drain Bias (M3)
9
8
7
6
5
4
3
2
1
0
V1=V2=V3<V4
V
0
10
20
0.5~0.9V
30
40
1.1V
V
50
V
60
DC power (mW)
22
Amplifier Stability Factor
Stability Factors
5
4
K>1
3
2
B1 > 0
1
0
140
150
160
170
180
190
200
Frequency (GHz)
• Unconditionally stable over 140-200GHz.
23
Large-Signal Setup
20 GHz
Signal
Source
x12
Freq.
Multiplier
Virginia
Diode Inc.
WR05
Variable
Attenuator
WR05
GGB
probes
0.2dB loss
WR05WR10
On-wafer DUT
Power
Meter
Erikson
Instruments.
PIN= -20dBm ~ +15dBm
Freq= 153GHz ~175GHz
• Power correction: Insertion calibration using W/G
THRU & On-wafer THRU
24
25
10
Psat= +6.3dBm
20
15
5
oP1dB= +1.5dBm
10
0
-5
Peak PAE= 8.4%
5
-10
0
-15
-20
-15
-10
-5
0
Pout (dBm), Gain (dB)
Power Added Efficiency (%)
Large-Signal Characteristics
freq= 153GHz
PDC= 25.5mW
0.65V
1.1V
5
Pin (dBm)
25
Comparison of Measured S21
S21 (dB)
10
S21 from VNA Meas.
S21 from Power Meas.
8
6
4
2
0
140
150
160
170
180
190
200
Frequency (GHz)
• VNA Measurement: Full 2-port TRL calibration
• Power Measurement: Insertion calibration
26
Performance Summary
Technology 65nm digital CMOS
Topology
3-stage Common-source
Center freq 150GHz
3dB BW
27GHz
Peak Gain
8.2dB
Input RL
-7.4dB
Output RL
-13.6dB
DC Power
25.5mW
P1dB
+1.5dBm
Psat
+6.3dBm
27
Conclusion
• Minimalistic Circuit Design Strategy
• “Design-rule Compliant” Transmission Line
Structure and Modeling
• Linear/Power measurement up to 200GHz
• Highest frequency CMOS amplifier reported to date
28
Acknowledgement
• IBM for chip fabrication and support
• OML Inc.
• This work was supported by the NSF under grants
CNS-0520335 and ECS-0636621
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