Transcript ECE 545 Lecture 8 Algorithmic State Machines Sorting Example ECE 545 – Introduction to VHDL George Mason University.

ECE 545
Lecture 8
Algorithmic State Machines
Sorting Example
ECE 545 – Introduction to VHDL
George Mason University
Sources & Required Reading
• Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design
Chapter 8.10
Algorithmic State Machine (ASM) Charts
Chapter 10.2.6
Sort Operation
(handouts distributed in class)
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Algorithmic State Machine (ASM)
Charts
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Algorithmic State Machine
Algorithmic State Machine –
representation of a Finite State Machine
suitable for FSMs with a larger number of
inputs and outputs compared to FSMs
expressed using state diagrams and state
tables.
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Elements used in ASM charts (1)
State name
Output signals
or actions
(Moore type)
0 (False)
(a) State box
Condition
expression
1 (True)
(b) Decision box
Conditional outputs
or actions (Mealy type)
(c) Conditional output box
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Elements used in ASM charts (2)
• State box – represents a state.
Equivalent to a node in a state diagram or a row
in a state table.
Moore type outputs are listed inside of the box. It
is customary to write only the name of the signal
that has to be asserted in the given state, e.g., z
instead of z=1. Also, it might be useful to write an
action to be taken, e.g., Count = Count + 1, and
only later translate it to asserting a control signal
that causes a given action to take place.
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Elements used in ASM charts (3)
• Decision box – indicates that a given condition is
to be tested and the exit path is to be chosen
accordingly
The condition expression consists of one or more
inputs to the FSM.
• Conditional output box – denotes output
signals that are of the Mealy type.
The condition that determines whether such
outputs are generated is specified in the decision
box.
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Moore FSM – Example 1: State diagram
Reset
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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ASM Chart for Moore FSM – Example 1
Reset
A
0
w
1
B
0
w
1
C
z
0
ECE 545 – Introduction to VHDL
w
1
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Mealy FSM – Example 2: State diagram
Reset
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
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ASM Chart for Mealy FSM – Example 2
Reset
A
0
w
1
B
z
0
ECE 545 – Introduction to VHDL
w
1
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Control Unit Example: Arbiter (1)
reset
g1
r1
r2
Arbiter
g2
g3
r3
clock
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Control Unit Example: Arbiter (2)
000
Reset
Idle
0xx
1xx
gnt1 g1 = 1
x0x
1xx
01x
gnt2 g2 = 1
xx0
x1x
001
gnt3 g3 = 1
xx1
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Control Unit Example: Arbiter (3)
r 1r 2 r 3
Reset
Idle
r1
r1
gnt1 g1 = 1
r2
r1
r 1r 2
gnt2 g2 = 1
r3
r2
r 1r 2 r 3
gnt3 g3 = 1
r3
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ASM Chart for Control Unit - Example 3
Reset
Idle
r1
1
gnt1
0
1
g1
r2
1
gnt2
g2
r3
r2
0
1
1
gnt3
g3
ECE 545 – Introduction to VHDL
0
1
0
0
r1
0
r3
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Digital System Design
with VHDL
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Structure of a Typical Digital System
Data Inputs
Execution
Unit
(Datapath)
Data Outputs
ECE 545 – Introduction to VHDL
Control Inputs
Control
Signals
Control
Unit
(Control)
Control Outputs
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Hardware Design with RTL VHDL
Interface
Pseudocode
Control Unit
Execution Unit
Block
diagram
VHDL code
ECE 545 – Introduction to VHDL
Block
diagram
VHDL code
ASM
VHDL code
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Sorting
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Sorting - Required Interface
Clock
Resetn
N
N
DataIn
DataOut
L
RAdd
Sort
Done
WrInit
S
(0=initialization
1=computations)
Rd
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Simulation results for the sort operation (1)
Loading the registers and starting sorting
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Simulation results for the sort operation (2)
Completing sorting and reading out registers
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Sorting - Example
Before
sorting
address
0
1
2
3
Legend:
3
2
4
1
During Sorting
i=0
j=1
i=0
j=2
i=0
j=3
i=1
j=2
i=1
j=3
i=2
j=3
3
2
4
1
2
3
4
1
2
3
4
1
1
3
4
2
1
3
4
2
1
2
4
3
position of memory
indexed by i
ECE 545 – Introduction to VHDL
Ri
position of memory
indexed by j
After
sorting
1
2
3
4
Rj
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Pseudocode for the sort operation
for i = 0 to k – 2 do
A = Ri ;
for j = i + 1 to k – 1 do
B = Rj ;
if B < A then
Ri = B ;
Rj = A ;
A = Ri ;
end if ;
end for;
end for;
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