Timing and Event System S. Allison, M. Browne, B. Dalesio, J.

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Transcript Timing and Event System S. Allison, M. Browne, B. Dalesio, J.

Timing and Event System
S. Allison, M. Browne, B. Dalesio, J. Dusatko,
R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S.
Norum, D. Rogind, H. Shoaee, M. Zelazny
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Outline
Overview – HW and Reqts
Hardware Test Stand
Long-Haul Fiber Issues and Plans
Outstanding Software Issues and Tasks
Wish List
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Hardware Block Diagram
2007 Commissioning
Modulator
Triggers
Existing
Control
System
RF
Timing
Future
MPS
Beam Path
Acq and BPM FEE
Calibration
Triggers
Timing
Crate
F F P
E
360Hz
A A N
Fiducial V
119MHz
Clock
I
O
N N E
G
1 2 T C
Beam Rate,
Beam Path
E
V
... R
3 1 1 1
8
…
Apr 25, 2007
EPICS Collaboration Meeting
Acc and
Standby
Triggers
E
V
LLRF R
Crate 1
E
V
R
2
E
I
V
O
R
C
3
Fiber Distribution:
Timing Pattern, Timestamp, Event Codes
Trigger
F E C I
Laser
Steering A V A O
N R M C
Crate
E I
BPM V O
Crates R C
PADs and PACs
C
A
M
8
I
O
C
8
TORO FEE
F
E I
Toro
A
Farc
V O
Crate N R C
4
Triggers
Profile E C C I
Monitor V A A O
R MM C
Crate
E
V
… R
1 1 2 1
4
…
Triggers
C
A
M
7
Stephanie Allison
[email protected]
C
A
M
8
I
O
C
4
Micro-Research Finland Oy
Event Generator (EVG-200)
SLAC PNET Receiver
Receives the MPG
broadcast sent to SLC
micros and passes it to
the EVG
SFP transceiver
• Optical signal to RF input
EVRs (fan-outs) • Event clock
• divided from RF
• /1*,/4, ... /12
Line syncronisation input
360 Hz
*SLAC addition
Apr 25, 2007
EPICS Collaboration Meeting
EVR Fan Out module
Stephanie Allison
[email protected]
Micro-Research Finland Oy
SFP transceiver
• Optical signal from
EVG (or fan-out)
Programmable outputs
• 5(3) TTL level
• 2 LVPECL level
External trigger input
Recovered RF
output
Event Receiver – PMC version
Apr 25, 2007
EPICS Collaboration Meeting
Event Receiver (EVR-200-RF)
Stephanie Allison
[email protected]
Modifications to EVG
119MHz clock input
In the absence of a ÷1 input, a daughterboard
was made containing a clock receiver IC to allow
us to input 119MHz directly
EVG AC-line input
360Hz fiducial input was rerouted with firmware
change to avoid addition of jitter from internal 10
kHz clock and phase shifter
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Tallies for 2007, Plans for Next Phase
# EVRs = 31 installed (mostly PMC)
Add 60 more EVRs - 34 VME, 26 PMC
# IOCs with EVRs = 28
Add 40 more IOCs with EVRs
# EVR Fanouts = 4
Add 5 more fanouts (1 every 200m)
# Hardware Triggers = 120+
All TTL except 2 NIM triggers for QDCs
Most require short cables (except LLRF)
Add ? more
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Timing Requirements
Maximum trigger rate
Clock frequency
Clock precision
Coarse step size
Delay range
Fine step size
Max timing jitter w.r.t. clock
Differential error, location to location
Long term stability
Apr 25, 2007
EPICS Collaboration Meeting
360 Hz
119 MHz
20 ps
8.4 ns ± 20 ps
>1 sec
20 ps
2 ps rms
8 ns
20 ps
Stephanie Allison
[email protected]
Event System Requirements
Event Generator IOC:
Send out proper event codes at 360Hz based on:
PNET pattern input (beam code and bits that define beam path
and other conditions)
Add LCLS conditions such as BPM calibration on off-beam
pulses , diagnostic pulse etc.
Future – event codes also based on new MPS and user
input
Send out system timestamp with encoded pulse ID from
PNET
Send out PNET pattern to be used by SLC-aware IOCs
Manage user-defined beam-synchronous acquisition
measurement definitions (event definition or EDEF)
Check for match between user EDEFs and input PNET
pattern at 360Hz and tag matches in outgoing pattern
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Event System Requirements, cont
Event Receiver IOC:
Set trigger delays, pulse widths, and enable/disable via
user requests (not yet done on a pulse-by-pulse basis)
Set event code per trigger (triggering done in HW when
event code received)
Receive event pattern 8.3 msec before corresponding
pulse
Perform beam-synchronous acquisition based on tags
set by EVG in the event pattern
Perform beam-synchronous acquisition for the SLCaware IOC based on the PNET part of the event pattern
Process pre-defined records when specific event codes
are received (not yet available – bug!)
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
EVG Event Time Line – 4 Fiducials
360Hz
Fiducial
F3 (n=3)
F1 (n=1)
2.8
R1
F2 (n=2)
5.6
R2
8.3 9.3
R3
Receive Fn+3 PNET,
determine Fn+3 LCLSP0
pattern, and advance
pipeline (n-2->n-1->n)
P1
P2
P3
L0
Set Event Codes in
Other RAM based on the E1
L1
E2
L2
E3
F0 (n=0)
Time (msec) 0 1.0
HW starts sending
R0
event codes, starting
with fiducial event code
Send LCLS pattern
L3
E4
last patterns for Fn+1
120Hz BEAM
B-3
Apr 25, 2007
EPICS Collaboration Meeting
B0
Stephanie Allison
[email protected]
Trigger Event Time Line – 1 Beam Pulse (B0)
Record processing (event, interrupt)
Hardware Triggers
Triggering
Event Codes
Event Timestamp, Start
pattern records,
and BSA ready
Receive pattern for
3 pulses ahead
Kly Standby Beam
Acq
Kly Accel Trigger
Fiducial Event
Received
Fiducial
B0
F3
Time (usec)
Apr 25, 2007
EPICS Collaboration Meeting
0
18
0.3 100
500
1023
Stephanie Allison
[email protected]
Trigger Control Display
EVG Displays
Hardware Test Stand
RF Gen
SLC trig
syncer
EVR Output
119MHz
Event
Generator
Pulse
Gen
(Trigger Signal)
Optical Fiber
Clk
Event
Receiver
AC Input
Trigger Out
Event Trig0
SLC trig
syncer
Delay between fid to trigger:
Minimum intrinsic
system delay +
adjustable value
Seq1 Trig
EVG Input
(360Hz fiducial)
VMEbus
VMEbus
VME
CPU
VME
CPU
Test System Topology
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Timing Jitter Test Results
Agilent 54845A
EVR jitter
w.r.t. fiducial
30 min.
PDU jitter
w.r.t. fiducial
13 ps rms jitter
13 ps rms jitter
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Event System HW: Long-Haul Dist.
For the next phase, the biggest challenge is LongHaul distribution of timing data via the Fiber-Optical
(F-O) Links
Why?
MRF Event System is designed around Multi-Mode SFP
(Small Form-Factor Pluggable) F-O links which allow a
maximum fiber length of ~300 meters
Our requirements include runs of several Kilometers (at
least)
Cannot daisy-chain the event F-O links: exceeds the
jitter budget
Temperature effects on long fibers – drift, but how bad?
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Event System HW: Long-Haul Dist.
Proposed Solution: New HW and some testing
Single-Mode, pin-compatible SFP modules are commercially
available (Agilent ACFT-57R5)
All us to go ~10KM
Should plug right into our event system HW
Still does not solve temperature-induced phase-drift
problem
Propose to solve by either/and:
Running Long Fiber in temperature-controlled environment
Re-Syncing EVRs to a locally-distributed 119MHz source
Long-haul fiber test:
Function of Single-Mode SFP Modules
Drift, Trigger time jitter, Phase Noise
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Event System – Long-Haul Fiber System Test
1.5KM SM Fiber
EVG
Fiber
Fanout
MCC
Optical
Coupler
1.5KM SM Fiber
Trig
EVR_1
RF Clk
(119MHz)
476MHz
Clk/Trig
Sync Chassis
Compare:
- Jitter
- Phase Noise
- Phase Drift
Fiducial
Trig
EVR_2
3M MM Fiber
RF Clk
(119MHz)
All Components located
in RF Hut
119MHz
Ref Clk
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Issues and Tasks
Outstanding problem (presumably software) where CPU hangs when
EVR interrupts are enabled. Some IOCs running without interrupts
(hardware triggers but without timestamps, BSA, or event code IRQs).
Outstanding bug with IRQ processing on VME EVRs
Software not yet in place to handle hardware and communication
errors.
Changing an event code for a specific trigger requires a change in the
delay to trigger at the same time – need database to automate the
change
Need generic timing delay scan software that works for most device
types
Need to get status of RF clock into the system (external interface)
Ability to change trigger attributes on a pulse-by-pulse basis using
simple conditional expressions
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]
Wish List
When 2 event codes trigger a device on the
same pulse, the second event restarts the
delay. Wish the second event would be
ignored instead.
Interrupt from the EVG on fiducial trigger
(AC line trigger)
Apr 25, 2007
EPICS Collaboration Meeting
Stephanie Allison
[email protected]