EE 5340 Semiconductor Device Theory Lecture 15 – Spring 2011 Professor Ronald L.
Download
Report
Transcript EE 5340 Semiconductor Device Theory Lecture 15 – Spring 2011 Professor Ronald L.
EE 5340
Semiconductor Device Theory
Lecture 15 – Spring 2011
Professor Ronald L. Carter
[email protected]
http://www.uta.edu/ronc
Forward Bias Energy Bands
nnon equil ni expEFn EFi / kT np np 0 eVa Vt 1
q(Vbi-Va)
Imref, EFn
Ec
EFN
EFi
EFP qVa
Imref, EFp
pnon equil ni exp EFi EFp / kT pn pn0 eVa
-xpc
©rlc L15-10Mar2011
-xp
0
xn
Ev
Vt
1
x
xnc
2
Law of the junction: “Remember
to follow the minority carriers”
N N
p
n
po
a
d V ln
no .
Vbi Vt ln
V
ln
t
t
n2
pno
n
po
i
pno npo
- Vbi
,
Invert to get
exp
ppo nno
Vt
pn np
Va - Vbi
and when Va 0,
exp
pp nn
Vt
©rlc L15-10Mar2011
3
Law of the
junction (cont.)
Switched to non - eq. not'n for Va 0 .
So pn pno pn , nn nno nn ,
and np npo np , pp ppo pp .
Assume nn pn and np pp .
Assume low - level injection
pp ppo Na and nn nno Nd
©rlc L15-10Mar2011
4
Law of the
junction (cont.)
So for pn ppe
We have pn
Va -Vbi
Vt
npo
nno
ppo e
and npo nno e
Va
Vt
the Law of the Junction
Va
pnnn x ni2e Vt ,
n
©rlc L15-10Mar2011
also ppnp
ni2
nno
e
xp
Vbi
Vt
Va
Vt
Va
ni2e Vt
5
Injection
Conditions
Va - Vbi
giving
pno pn ppo exp
Vt
Va -Vbi
-Vbi
pn ppoe Vt pno , pno ppoe Vt ,
Va
so pn pno exp 1, at x xn
Vt
Va
sim. np npo exp 1, at x xp
V
t
©rlc L15-10Mar2011
6
Ideal Junction
Theory
•
•
•
•
•
Assumptions
Ex = 0 in the chg neutral reg. (CNR)
MB statistics are applicable
Neglect gen/rec in depl reg (DR)
Low level injection applies so that
np < ppo for -xpc < x < -xp, and
pn < nno for xn < x < xnc
Steady State conditions
©rlc L15-10Mar2011
7
Ideal Junction Theory (cont.)
p n
In the steadystate(static)case,
0 , and
t t
applyingthe ContinuityEquationto the CNR
p dp 1
0
Jp , x n x x nc , and
t dt q
n dn 1
0
Jn , - x pc x x p
t dt q
©rlc L15-10Mar2011
8
Ideal Junction
Theory (cont.)
dn
Since Ex 0 in the CNR, Jnx qDn
dx
dp
and Jpx qDp
giving
dx
d2 pn
dx2
2
pn
0, for xn x xnc , and
Dp p
d np
dx2
©rlc L15-10Mar2011
np
Dn n
0, for - xpc x xp
9
Ideal Junction
Theory (cont.)
Define
2
2
Ln Dn n and Lp Dp p . So
pn x Ae
x
Lp
Be
x
np x Ce Ln De
x
x
Lp
, xn x xnc
Ln , - x x x .
pc
p
pn xn np xp
with B.C.
eVa Vt 1 ,
pno
npo
and pn xnc np xpc 0, (contacts )
©rlc L15-10Mar2011
10
Diffusion Length model
Diffusion Length, L (microns)
1000.0
electrons
holes
100.0
10.0
1.0
L = (D)1/2
Diffusion Coeff. is
Pierret* model
min
45 sec
2
1 7.7E 18Nim 4.5E 36Nim
0.1
1.E+13 1.E+14 1.E+15 1.E+16 1.E+17 1.E+18 1.E+19 1.E+20
Doping Concentration (cm^-3)
©rlc L15-10Mar2011
11
Minority hole lifetimes
Mark E. Law, E. Solley,
M. Liang, and Dorothea
E. Burk, “SelfConsistent Model of
Minority-Carrier
Lifetime, Diffusion
Length, and Mobility,
IEEE ELECTRON
DEVICE LETTERS,
VOL. 12, NO. 8,
AUGUST 1991
The parameters used in
the fit are
τo = 10 μs,
Nref = 1×1017/cm2, and
CA = 1.8×10-31cm6/s.
τp
©rlc L15-10Mar2011
τo
1 ND Nref τ oC AND2
12
Minority electron lifetimes
Mark E. Law, E. Solley,
M. Liang, and Dorothea
E. Burk, “SelfConsistent Model of
Minority-Carrier
Lifetime, Diffusion
Length, and Mobility,
IEEE ELECTRON
DEVICE LETTERS,
VOL. 12, NO. 8,
AUGUST 1991
The parameters used in
the fit are
τo = 30 μs,
Nref = 1×1017/cm2, and
CA = 8.3×10-32 cm6/s.
τn
©rlc L15-10Mar2011
τo
1 ND Nref τ oC AND2
13
Excess minority
carrier distr fctn
For xn x xnc , Wn xnc xn ,
sinh xnc x Lp Va V
e t 1
pn x pno
sinh Wn Lp
and for - xpc x xp , Wp xpc xp ,
sinh x xpc Ln Va V
e t 1
np x npo
sinh Wp Ln
©rlc L15-10Mar2011
14
Forward Bias
Energy Bands
nnon equil ni expEFn EFi / kT np np 0 eVa Vt 1
q(Vbi-Va)
Imref, EFn
Ec
EFN
EFi
EFP qVa
Imref, EFp
pnon equil ni exp EFi EFp / kT pn pn0 eVa
-xpc
©rlc L15-10Mar2011
-xp
0
xn
Ev
Vt
xnc
1
x
15
Carrier
Injection
ln(carrier conc)
ln Na
Va V
t
np xp npo e
1
~Va/Vt
ln Nd
Va V
t
pn xn pno e
1
ln ni
~Va/Vt
ln ni2/Nd
ln ni2/Na
-xpc
©rlc L15-10Mar2011
-xp 0
xn
x
xnc
16
Minority carrier
currents
Jp x
dpn
qDp dx ,
2
qni Dp
for xn x xnc
cosh xnc x Lp Va V
e t 1
NdLp
sinh Wn Lp
Jn x qDn
d np
dx
, for - xpc x xp
cosh x xpc Ln Va V
e t 1
NaLn
sinh Wp Ln
©rlc L15-10Mar2011
qni2Dn
17
Evaluating the
diode current
Assu min g no gen/rec in DR, then
Va V
J Jp xn Jn xp Js e t 1
where Js Jsn Jsp with definition s
Jsn / sp
©rlc L15-10Mar2011
2
qni
Dn / p
Na / dLn / p
coth Wp / n Ln / p
18
Special cases for
the diode current
Long diode : Wn Lp , or Wp Ln
Jsn
2
qni
Dn
2 Dp
, and Jsp qni
NaLn
NdLp
Short diode : Wn Lp , or Wp Ln
Jsn
qni2
©rlc L15-10Mar2011
Dn
2 Dp
, and Jsp qni
NaWp
NdWn
19
Ideal diode
equation
• Assumptions:
–
–
–
–
–
low-level injection
Maxwell Boltzman statistics
Depletion approximation
Neglect gen/rec effects in DR
Steady-state solution only
• Current dens, Jx = Js expd(Va/Vt)
– where expd(x) = [exp(x) -1]
©rlc L15-10Mar2011
20
Ideal diode
equation (cont.)
• Js = Js,p + Js,n = hole curr + ele curr
Js,p = qni2Dp coth(Wn/Lp)/(NdLp)
= qni2Dp/(NdWn), Wn << Lp, “short”
= qni2Dp/(NdLp), Wn >> Lp, “long”
Js,n = qni2Dn coth(Wp/Ln)/(NaLn)
= qni2Dn/(NaWp), Wp << Ln, “short”
= qni2Dn/(NaLn), Wp >> Ln, “long”
Js,n << Js,p when Na >> Nd
©rlc L15-10Mar2011
21
Diffnt’l, one-sided
diode conductance
Static (steadystate) diode I-V
characteristic
ID
Va
ID Is exp d
Vt
dID
gd
dVa VQ
IQ
Va
©rlc L15-10Mar2011
VQ
22
Diffnt’l, one-sided
diode cond. (cont.)
ID JA JsA exp dVa Vt Is exp dVa Vt
Is exp VQ Vt
dID
gd VQ
. If Va Vt ,
Vt
dVa VQ
then gd VQ
IDQ
, where IDQ ID VQ .
Vt
Vt
1
The diode resistance , rd VQ
gd IDQ
©rlc L15-10Mar2011
23
Charge distr in a (1sided) short diode
pn
Wn = xnc- xn • Assume Nd << Na
• The sinh (see L10)
pn(xn)
excess minority
carrier distribution
Q’p
becomes linear for
Wn << Lp
pn(xn)=pn0expd(Va/Vt)
x
• Total chg = Q’p =
x
xnc
Q’p = qpn(xn)Wn/2
©rlc L15-10Mar2011
n
24
Charge distr in a 1sided short diode
pn p (x ,V +V)• Assume Quasi-static
n n a
charge distributions
pn(xn,Va)
• Q’p = +qpn(xn,Va)Wn/2
Q’p • Q’ =q(W/2) x
p
Q’p
{pn(xn,Va+V)
xn
©rlc L15-10Mar2011
xnc
pn(xn,Va)}
x• Wn = xnc - xn (Va)
25
Cap. of a (1-sided)
short diode (cont.)
Qp Q'p A, A diode area. Define Cd
d qApn (xn )Wn
d
dVa
2
dVa
dQp
dVa
qApn0 Wn
exp
d
V
V
a t
2
IDQ Wn2 IDQ
When Va Vt , Cd VQ
transit .
Vt 2Dp
Vt
xnc
Wn2
So, rd VQ Cd VQ transit q
dx
Jp
2Dp
x
pn
n
©rlc L15-10Mar2011
26
Evaluating the diode current density
Assuming no gen/rec in DR, then
Va Vt
iD Va Jp x n Jn x p A Js A e 1
where Js Jsn Jsp withthe definitions
Dn
Jsn qn
cothWp L n ,
NaL n
2 Dp
Jsp qni
cothWn L p
NdL p
2
i
©rlc L15-10Mar2011
27
General timeconstant
For all diodes, long or short, the conductanc e
gd VQ
d Jn Jp
dID
A
gn gp
dVa VQ
dVa VQ
There is always a characteri stic time so that
dQp
dQn
pgp Cp
, and n gn Cn
, and the
dVa
dVa
total diode capacitanc e C Cp Cn
©rlc L15-10Mar2011
28
General timeconstant (cont.)
For the short diode side, p p,trans
Wn2
,
2Dp
and n n,trans
2
Wp
2Dn
, the
physical charge transit times. For the
long diode side, p p0 and n n0 ,
the respective min. carr. life - times.
©rlc L15-10Mar2011
29
General timeconstant (cont.)
Practical diodes are usually one - sided
The effective transition time is the
1
1
1
average given by
and
F min transit
Cd gd F
©rlc L15-10Mar2011
30
References
1 and M&KDevice
Electronics for Integrated
Circuits, 2 ed., by Muller and Kamins, Wiley,
New York, 1986. See Semiconductor Device
Fundamentals, by Pierret, Addison-Wesley,
1996, for another treatment of the model.
2Physics of Semiconductor Devices, by S. M. Sze,
Wiley, New York, 1981.
3 and **Semiconductor Physics & Devices, 2nd ed.,
by Neamen, Irwin, Chicago, 1997.
Fundamentals of Semiconductor Theory and
Device Physics, by Shyh Wang, Prentice Hall,
1989.
©rlc L15-10Mar2011
31