Transcript Design and Implementation of a Link Level Adaptive Software Radio Information & Telecommunication Technology Center Richard A.

Design and Implementation
of a
Link Level Adaptive Software Radio
Information & Telecommunication
Technology Center
Richard A. Killoy
May 27, 1999
Presentation Overview
•
•
•
•
Brief Overview of RDRN
Motivation - Why build this radio?
Transceiver System Level Description
Transmit and Receive Chain
Implementation
• Summary & Future Work
RDRN Overview
• Design High-Speed
wireless ATM/IP
Comm. Systems with
Network and DLL
adaptability which are
rapidly deployable.
• Sponsored by
DARPA’s GLO-MO
initiative
This years goals:
• Channel Estimation &
Link Adaptation
• Software Radios
• Adaptive Networking
• Resource Reservation
Styles
• Comparative
Performance Evaluation
of IP vs. ATM
RDRN System Architecture
Three Overlaid Radio Networks:
• Low-Power Orderwire for
signaling
• High Capacity wireless ATM
backbone
• Cellular-like Radio
Network for
ATM access
to end users
1-8 Mbps
Mobile End User Node
Ethernet
Radio Controller
and Transceiver
Linux Host
AT M Network
High Data Rate
Edge Node
10-100 Mbit/sec
1-8 Mbps
Mobile End User Node
Ethernet
Radio Controller
and Transceiver
Linux Host
Motivation
Goal
Solution Strategy Employed
Channel Estimation Algorithms
The use of adaptive equalization,
functioning as channel estimators.
Link Level Adaptation Algorithms
Software radio allows us the flexibility to
change link level parameters.
Radios to Test, Evaluate, and Validate
Software radios implementing the use of
the channel estimation and link-level
high-speed ADC and various DSP chips.
algorithms
These chips can be programmed
dynamically via a PowerPC processor.
Adaptive Parameter
Allowable Values
RF Section
Transmit Power Control, TPC
5 dBm to 25 dBm in 2 dB increments
Carrier Frequency
Carrier frequency can be tuned within RF
bandwidth in increments of 10 MHz
*RF Front End
Static Design, but supports 5.3 GHz, 2.4
GHz, and 1.2 GHz band.
Physical Layer
Modulation format
BPSK, QPSK
Data Rate
1, 2, 4 MSPS
Data Link Layer
FEC
Limited by complexity of combinational
logic circuit implemented in Alteras
Multiple Access Scheme
TDMA, FDMA or hybrid combination
of both
RF Preamble for TDMA
Limited by length of time slot
HDLC Frame Length
Limited by Ethernet Packet Size, 1.5 kB
Complete System Including Housing
RF Front End
Tx IF/RF InterConn.
Antenna Ports
Main Digital
Board
Rx IF/RF
Interconnects
BERT
Ports
PowerPC
Microprocessor
Board
Transmitter Requirements

Transmit within RF bands at 5.3 GHz, 2.4 GHz, and 1.2 GHz

Frequency Agility – ability to select from multiple channels within each RF band

Average power output of +30 dBm (1W) from each antenna

RF Bandwidth = 100 MHz

Channel BW = 10 MHz

Selectable QPSK or BPSK modulation

Symbol Rates of 1, 2, or 4 Msymbols/sec

Multiple Access: FDD with TDMA/FDMA

Transmit Power Control ( 2 dB steps from 5 dBm to 25 dBm)

Transmit Power ON/OFF capability (TDMA)

TxData received from PowerPC

LO Spurious level = -28 dBm

LO Phase Noise <= -130 dBc/Hz at 50 MHZ offset
Transmitter System Level Diagram
Software Selectable,
Sectored Beamforming
Beamforming Control
Transmit Power Control
Ethernet
Linux
Host
PowerPC
Digital
Formatting
Software Control of
Initialization, Transmit
Power and
Beamforming
IF
240 MHz
RF
5.06 GHz
5.3 GHz QuadSectored
Antenna
Spectrum Utilization
5.35 GHz
50 MHz
5.25 GHz
10 MHz
5 MHz
a
b
c
a
d
b
c
d
5.3 GHz
4 TX Channels
4 RX Channels
1 Channel = 10 MHz
RF Band = 100 MHz
Receiver Requirements

Receive within RF bands at 5.3 GHz, 2.4 GHz and 1.2 GHz

Frequency Agility – ability to select from four channels within RF band

Full Duplex Operation

Digital IF Architecture (subsampling)

Demodulate QPSK or BPSK modulation

Receiver band selectivity = 100 MHz

Receiver channel selectivity = 10 MHz

Symbol Rates from 1, 2 or 4 MSymbols/sec

Dynamically configurable – must be a multidimensional radio with varying
software profiles (Software Radio)

RxData passed to PowerPC

NFmax <= 10 dB

Receiver sensitivity = -85 dBm

Dynamic Range = 60 dB
Receiver System Level Diagram
P atc h
A ntenna
A daptivity, Programming
and Initiali zation
A GC Control
RF
IF
Digi tal Radio
P owerPC
E thernet
5.23 GHz
A DC
DQT
DCL
s tore rec overed s ymbols for c hannel
es ti mation
Linux
Hos t
Benefits to Digital Demodulation
•
•
•
•
No need for tuning filters
Can Construct Linear Phase Filters
Flexible BW selection
Multiple Modulation Formats can be
supported
• System can be simulated “exactly”
• Multiple Radio “Personalities” as easy as
setting up tables
Control Bus Architecture



Control Bus is a serial bus controlling:
PLL programming
Programmable Attenuators
Beamforming
5
EX[0..3]
AT TEN[0..4]
4
PowerPC
Data
BF[0..4]
5
Digital
Formatting Digital
Data
10
A[0..2]
D[0..6]
Add&Data Bus for
demodulator programming
5
IF
Analog
TxSignal
I2C[0..4] - for programming
PLL's
RF
Power Section
+12  +9, +5, +3.3V
240 MHz PLL
& VCO
Tx IF Stage
10MHz
Oscillator
AGC Amp
Rx IF Stage
IF Test
Point
ADC,
fs=40MSPS
BusControl
Altera
40MHz CLK &
CLK Drvr
Programmable
DQT and DCL
Bit Error Rate (BERT) Ports
AGC Power Level
Indicators
Tx Source
Select
(PPC, PN, BERT)
5.3 GHz Modular RF Front End
IF Output
Rx Ant.
Port
10 MHz Ref.
Input
PLL’s
IF Input
VCO’s
Tx Ant.
Port
Average Power Requirements
Voltage [V]
Current [A]
Regulators (alone)
Analog Sections
9V sections
Total for Analog Sections
12
12
12
12
40m
120m
190m
350m
Power Needed
[W]
0.480
1.44
2.28
4.2
5V Digital.
(Quiescent Only)
3.3V Digital. Powering only
Altera’s (Quiescent Only)
Total Power for Digital
5V
1.6
8
3V
333m
1
9W
Total Power PPC (Quiescent),
datasheet claims 8W
Total Power
5W
12 V
1.52 A
18.2 W
Receiver Implementation
5.3GHz
Omni
Antenna
Patch has
selectivity of
130 MHz BW
MGA86576
-90dBm
+18dB
NF=2dB
P1dB=+5dBm
IIP3=+16dBm
5.23 GHz LO
PLL & VCO
-72dBm
-64dBm
-72dBm
-73dBm
-53dBm
LO
MGA82563
LPF
+8dB
NF=2.5dB
P1dB=+17dBm
IIP3=+31dBm
MSA0611
+20dB
HMC218MS8
Dbl Balan. MIxer
CLoss = -8dB
P1dB=+2dBm
80 MHz Fc
1dB@70M
40dB@120M
to IF stage
NF=3dB
P1dB=+2dBm
Patch Antenna Sub-Assembly
Power Supply
1W Power
Amplifier
Integrated BPF
Patch Antenna
View of RF Receiver
10MHz
Reference Input
RF Output,
to IF section
VCO
RF Mixer
x2 Frequency
Doubler
from LNA &
Antenna
PLL
Input Signal Levels Throughout Receive Chain
Stages within Receive Chain – all Input Power Levels in dBm
PTX @
1W
Desired
Signal –
Min
Desired
Signal -Max.
Adjacent
Channel
at
10MHz
Offset
Tx
Signal
50M
offset,
1W,
50dB*
isolation
LNA
-90
82563
-72
Mixer
-64
LPF
-72
0611
-73
SAW
-53
AGC
-63
(+24)
BPF
-39
0611
-40
2011
-20
BPF
-2
ADC
-3
-26
-8
0
-8
-9
+11
+1
(-40)
“
“
“
“
“
-90
-72
-64
-72
-73
-53
-83
(+24)
-59
-60
-40
-22
-23
-26
-8
0
-8
-9
+11
-19
(-40)
-59
-60
-40
-22
-23
-20
-2*
+6
-2
(-40)
-42
-22
(-50)
-72
(+24)
-48
-49
-29
-11
-12
-72
(-40)
-112
-113
-93
-75
-76
Receive Signal Levels
Power Levels for Various Signals throughout Receive Stages
20
0
-20
Signal Level
[dBm]
-40
-60
Min. Rcr Signal
Max. Rcr Signal
Adj. Channel
Tx. Signal
-80
LNA
-100
0
2
4
6
Stage
8
10
12
System Noise Figure
Total Cascaded System Noise
Figure
2.5
2
Noise
Figure
[dB]
1.5
1
0.5
0
LNA
Amp1
Cable
LPF
Mixer
Cable
Amp2
Stage
Amp3
AGC
SAW
BPF
BPF
Amp4
Receiver, IF to ADC
-53dBm
-63dBm
-39dBm
-40dBm
-20dBm
-2dBm
-3dBm
SAW Filter
Sawtek 854665
RF2607
MSA0611
MGA2011
BPF
BPF
from RF
board
AGC
+20dB
+18dB
ADC
to Digital
Stage
12
NF=3dB
NF=3dB
70 MHz CF
+45dB to -35dB
12 bit
P1dB=+2dBm P1dB=+8dBm
10 MHz BW
NF = 5dB
Imped. Matching
Imped. Matching fs=40MSPS
Ins. Losss = -10 dB
Ins.Loss= -1dB
Ins.Loss= -1dB 80dB SFDR
input: -3dBm
Receiver, IF to ADC
AGC Amp.
+40dB Amplifier Chain
70MHz
SAW Filter
IF Testpoint,
-20dB down
IF Input,
from RF board
Aux. Input
AGC Output
A/D
Converter,
40MSPS
Digital Section
Bus Control
Altera
EPM7128S
to PPC
RxData & RxCLK
10
10
2
Address & Data Bus
for programming
from ADC
12
I
Altera
EPM7128S
DQT
HSP50110
10
10
Q
I
Altera
EPM7128S
10
10
Q
DCL
HSP50210
10
30
Synch.
15
20
Hard
Disk
Logic Analyzer
20
Altera
EPM7128S
Digital Quadrature Tuner
Digital Costas Loop
Digital Section
SigProc3
Altera
40Mhz
Oscillator
CLK
Driver
BusCtrl Altera
ADC,
fs=40MSPS
Wactchdog
IC—for Power
Reset
SigProc1
Altera
DCL
SigProc2
Altera
BERT
Ports
AGC LED Level
Indicators
DQT
Source Selector
Transmitter Implementation
(Baseband to IF)
240 MHz LO
PLL & VCO
SAWT EK 855092
240 MHz BPF
LO
PowerPC
Altera CPLD
EPM7128S-7
Source
Data
Format
1-8Mbits/sec
HDLC format
500K to
4 MSym/sec
+1dBm
LPF
I
MSA-1105
I
Quadrature
Modulator
Q
+14dBm
+13dB
+3dBm
+16dBm
MSA-1105
+13dB
Prog.
Atten
+12dBm
to RF
section
Q
1st Order
RC filter,
fc = 5MHz
RF2464
-11dB Loss
BW = 12MHz
P1dB=+17.5dBm
P1dB=+17.5dBm
NF=3.6dB
NF=3.6dB
IIP3=30dBm
IIP3=30dBm
-4dB Loss,
0-44dB
Atten. Range
Close Up View of Tx IF Stage
RF2464
Modulator
240MHz
PLL &
VCO
Oscillato
240MHz
r
SAW
10MHz
Oscillat
or
10MHz
10MHz
filter
Oscillator
Oscillat
Prog.
or
Attenuators
10MHz
Oscillator
10MHz
IF
Transmit
Output,
to RF
Board
Oscillat
Oscillat
or
10MHz
Drive Ckt
for Modulator
10MHz
Reference Outputs,
to RF Board
Oscillator
10MHz
Transmit RF Section
Software Selectable,
Sectored Beamforming
5.07 GHz LO
PLL & VCO
+12dBm
3dB
Pad
from
IF section
LO
+1dBm
+8dBm
MG82563
+7 dB
+15dBm
+12dBm
+31dBm
Power
Printed HairPin
Amp.
MG82563
BPF
MGA-85563
+7 dB
+19dB
P1dB=+17dBm
HMC218MS8,
P1dB=+16dBm
-3dB loss
NF=3dB
P
=+17dBm
Dbl. Bal.
IP3=+29dBm
100MHz BW
1dB
NF=3dB
Mixer
-28@400MHz BW NF=7.2dB
CLos s=8dB
-40@800MHz BW
5.3 GHz QuadSectored
Antenna
Transmit RF
IF Input
RF Mixer
Oscillato
r
PLL
10MHz
10MHz
Input
Oscillato
r
10MHz
Oscillato
r
10MHz
Oscillato
r 2.5 GHz
VCO
10MHz
Oscillato
r
10MHz
x2
Frequency
Doubler
RF Output,
to PA and
Antenna
Summary
• Software controlled radio with modular RF front ends for
use in channel estimation.
• High-Speed (up to 8 Mbps) wireless radio which is
capable of physical layer and data-link layer adaptability.
Future Work
• Use this radio “platform” to develop protocols and
algorithms to control the physical & data-link layer.
• Real time channel estimation and the use of these
parameters in the above adaptation algorithms.
Sub-Sampling
Spectrum
to be
sampled
How to choose fs ,
0
-70
70
F [MHZ]
convolved
with
samples
2 fH
2f
 fs  L
k 1
k
where themaximumvalue of k is :
k
-40
0
40
0
0.25fs fs/2
F [MHZ]
fs=40M
Digital
Spectrum
-fs/2
= 10M
f
fL
fH  fL
Decimation
Apparent useable BW
fs
Can Only see up to 2
Decimation creates new
“folding frequency”
Noise and possible
interferers aliased into
passband?--How much
attenuation? Use Alias
Profile
Digital Quadrature Tuner, detail
Digital Costas Loop, detail