9/20/6

MicroBaby A simple micro-controller encompassing all the basics

Start this class by organizing into groups.

Lecture 2 - Prog Model

1

Lecture Overview

 What is MicroBaby  The architecture  Addressing modes  Instructions  Internal registers and control signals 9/20/6 Lecture 2 - Prog Model 2

What is MicroBaby?

 Micro-Baby is a simple computer architecture, in fact, very simple.

  All microcontrollers and microprocessors are computer architectures, in most cases fairly simple ones.

In today’s world even microcontrollers are eons beyond basic.

9/20/6 Lecture 2 - Prog Model 3

Basic assumptions

 It is assumed that the reader possesses a basic understanding of the binary number system and the implementation of logic equations in digital logic using AND, OR, NAND, NOR, XOR and NOT gates.

 It is also assumed that the reader also has a somewhat beyond basic understanding of computer architecture.

9/20/6 Lecture 2 - Prog Model 4

Basic styles of architecture

    Micro-Baby is a accumulator based load-store architecture.

It embodies the essence of the principles of a RISC architecture.

All instruction execution results are left in the accumulator.

The accumulator based load-store architecture is the base processor architecture that all other architectures build upon 9/20/6 Lecture 2 - Prog Model 5

MicroBaby internal structure

 High level and high level internal structure Input Device Central Processing Unit Control Unit Arithmetic/Logic Unit Accumulator Memory Unit Output Device CPU ACC ALU Memory Data Bus 8 256 bytes Controller SR PC Instr Reg FF Reset Vector 8 8 Data Memory 256 bytes Instruction Memory 256 bytes Memory Address Bus 000000xx I/O addresses Memory Loader On startup 9/20/6 Lecture 2 - Prog Model 6

The memory modules

 Interface to the memory modules Data Address r/w ce 8 8 Memory RAM 9/20/6 Lecture 2 - Prog Model 7

The ALU

 Version 1 of the alu 8 mbALU Cout 8 A Add/Sub 8 B Mux 1 = B 0 = B’ AddSub Csel Cin Cin’ 8 AddSub 8 Cin A Logic Unit B F(3 dt 0) Csel(1 dt 0) 00 – Cin 01 – NOT Cin 10 – ‘0’ 11 – ‘1’ N Z All 0’s Sum 8 8 Mux 8 Lout Arlo 1 = Sum 0 = Lout 9/20/6 Lecture 2 - Prog Model 8

The datapath

 The datapath showing the internal data bus Aal Bbu Ldac Cout N Z Mux amuxtoacc Accumulator accout zero Mux bmuxout ALU alures DrAcc F(3 dt 0) AddSub Cin Arlo Csel Data Bus F function AND 1000 OR 1110 INV 0011 XOR 0110 Aal 1 = alures 0 = Dbus Bbu 1 = zero 0 = Dbus 9/20/6 Lecture 2 - Prog Model 9

The controller

 Version 2 of the conroller Controller SR Instr Reg PC unit Aal Bbu Ldacc Dracc AddSub Arlo Csel F(3 dt 0) Cin N Z Rst Fixval PC PCsel Program Counter incrementer 9/20/6 Lecture 2 - Prog Model 10

The instructions

    The instruction set Offers the basics Would like to have logical shift instruction Maybe rotate

I NSTR

LDA LDA

Op Code

1000 0010 1000 0001

STA

ADD 1010 0010 0100 0010

ADD

0100 0001 ADDC 0100 1010

ADDC

SUB 0100 1001 0101 0010

SUB

SUBC

SUBC

INC DEC AND

AND

OR

OR

INV XOR

XOR

CLRA

CLRC CSET

CMP CMP JMP 0101 0001 0111 0010 0111 0001 0100 1100 0100 0100 0101 1010 0101 1001 0101 1110 0101 1101 0101 1000 0101 0110 0101 0101 0100 1111 0100 0000 0100 1000 0100 1010 0100 1001 11cn zuuu Arg Na NA Addr Arg Addr Arg Na Addr Arg Na

2 nd by

Addr Arg Addr Addr Arg Addr Arg Addr Arg Addr Na Na Addr Arg Addr

Addr mode

Direct Immediate Direct

Direct

Immediate

Direct

Immediate

Direct

Immeddiate

Direct

Immeddiate

Inherent Inherent Direct

Immeddiate

Direct

Immeddiate

Inherent Direct

Immeddiate

Inherent

Inherent Inherent

Direct Immeddiate Direct

dpcsvec ecsvec/e2csvec

00000000 01001 / 01000 01100000 00101 9/20/6 Lecture 2 - Prog Model 11

Debugging the controller

 The controller encoding in the microcode needs debugging to insure correctness.

 Note the multiple control signals need to allow the architecture to function.

 Friday will be simulation demonstration and general discussion of microbaby and what it teaches. Along with discussion of MU0 9/20/6 Lecture 2 - Prog Model 12

General note on this class

 The only way the format of the class works is if the students participate.  After presentations a discussion will be lead to fill in the blanks from the presentations.



Attendance will be taken and will be incorporated into the grade.

9/20/6 Lecture 2 - Prog Model 13

Topics of talks

 Friday – continue with microbaby  Wednesday – Chapter 1 of text – setting the tone.

 Topic for beyond Friday will be shown Friday.

9/20/6 Lecture 2 - Prog Model 14

Topics for presentation next week

    Next Wednesday Jan 21st Group 1 – Chapter 1 of text    Processor architecture and organization Hardware Design Abstraction MU0 – a simple processor Group 2 – Chapter 1 of text  Processor design tradeoffs   RISC – organization – advantages – drawbacks Design for low power Discussion – compare and contrast MU0 to microbaby 9/20/6 Lecture 2 - Prog Model 15

Future topics

 The Acorn RISC – history of deployment, more details on company development and interaction with Apple, VLSI Technology. This led to Acorn RISC Machines, Ltd. which became ARM.

 Architectural inheritenance from the Berkeley RISC I and II. Details of the Berkeley RISC and its history 9/20/6 Lecture 2 - Prog Model 16

Future topics

    The ARM programmer’s model – what the programmer sees. (2 presentations) - This includes what is in the datapath and the structure of memory and I/O seen. Tools for assembler language programming.

It would be nice to have a “free” simulation tool for ARM about now. ARM Sim from the University of Victoria may be the one we use.

Free textbook is available online Also, wikipedia is a great source for information.

9/20/6 Lecture 2 - Prog Model 17

9/20/6 Lecture 2 - Prog Model 18

9/20/6 Lecture 2 - Prog Model 19

9/20/6 Lecture 2 - Prog Model 20

9/20/6 Lecture 2 - Prog Model 21

9/20/6 Lecture 2 - Prog Model 22

9/20/6 Lecture 2 - Prog Model 23

9/20/6 Lecture 2 - Prog Model 24