Transcript Chip Carrier Package as an Alternative for Known Good Die Raymond Kuang September 08, 2004

Chip Carrier Package as an
Alternative for Known Good
Die
Raymond Kuang
September 08, 2004
Driver for Known Good Die (KGD)
Applications which require integration of different
die technologies in one board (Multi-Chip- Package,
System-in-Package, etc) and where the cost of board
rework due to bad die is severe.
 Major markets are portable electronic products.
 The advent of small footprint packages like Chip Scale, Wafer
Scale, etc offers a low cost alternative for low end
applications.
 High end systems which require limited weight
and space.
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Limitation of KGD
High end KGD for high end application is difficult to
obtain.
 Limited to small I/O devices due to technical difficulties.
 Full screening through the fine bond pad pitch in today’s
sub-micron silicon technology is an issue.
Each die size for KGD normally requires custom
socket.
Marking for traceability, such as wafer lot, is not
possible.
 Mil-Std-883 requires traceability for Space Application
devices.
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Chip Carrier as an Alternative Solution
for KGD
17 mm
17 mm
Total Thickness : 1.847 mm
256 Bond fingers on edges of package
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Chip Carrier as an Alternative Solution
for KGD
 Advantages:
 Designed for high density I/O where bare die testing is
not technically and economically feasible.
 Testing and Programming the device through the package
terminal is reliable.
 Voltage and currents are controlled with the use of low socket
impedance.
 Testing and programming are same as package parts like
BGA or LGA. They are cost effective and reliable
 Can accommodate many die sizes in one Chip Carrier
package outline.
 No custom socket is needed for each die configuration.
 Can be marked for unit traceability (wafer lot#, etc).
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Chip Carrier as an Alternative Solution
for KGD… con’t
Features
Small Foot print.
 Can be used for both wire bond and flip chip version.
 Wire bond version.
 Smallest size is around bare die size + 6.5 mm.
 Flip Chip version.
Smallest size is bare die size + 5.0 mm.
Lead finger for wire bond use
Pads for Test/Programming use or BGA connection
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Chip Carrier as an Alternative Solution
for KGD… con’t
Two terminals available for each signal:
 External lead fingers on the top sides – for wire bond from
package to MCM use.
 Land grid pads at the bottom – primarily for test use. Can be
utilized for BGA connection to the MCM board also.
Chip Carrier material can be ceramic, organic or other
suitable materials.
 Multi-layer build-up substrate to enhance electrical performance
and routing for high density I/O applications.
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Method to Integrate into MCM
 Wire bond top lead fingers to system board to route
out signal.
 Chip Carrier must be attached using electrically non-
conductive epoxy to system board.
epoxy
Wire bond version
Flip Chip version
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Method to Integrate into MCM…con’t
Use the land pads at the bottom of the package.
 Chip Carrier can be connected using solder balls and reflow
to the system board.
Solder ball
Wire bond version
Solder ball
Flip Chip version
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Manufacturing Issue and solution
Major concern is contamination on external bond
fingers that may affect board level wire bonding
reliability.
 Due to poor handling at assembly and test, and equipment
cleanliness.
 use of contaminated finger cots in handling the unit, use of
contaminated perfluorocarbon bath at gross leak test, out
gassing from contaminated burn-in board, etc…
Handling-induced contamination can be prevented
by the use of clean vacuum pen to “pick and
place” the units.
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Manufacturing Issue and solution…
con’t
A good control to prevent contamination of
accessories like trays/boats, sockets, etc. use in the
assembly and test of the parts must be in place.
Use of low power microscope at visual inspection is
necessary.
Wet cleaning using Isopropyl Alcohol can be used to
remove most surface contamination induced during
assembly and test screening.
Recommended to do plasma cleaning prior to wire
bonding at Multi-Chip-Module or board level
assembly.
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Bond Finger Reliability at Board Level
Chip Carrier units were exposed to different handling
conditions, attached and wire bonded to a ceramic
package and aged at 150C environment. A bond pull
test was done to determine the interconnect
reliability.
Ceramic Land Grid Array Package
Gold bond
Ceramic Chip Carrier
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Reliability Evaluation… con’t
 Details
Bond Strength Test
Unit #
Carrier Bond Fingers Condition Prior
To Wire bond
2
No cleaning. Represents unit that go
through assembly and Mil-Std-883
Class S device screening with normal
handling
Wet clean after burn-in.
3
Plasma clean prior to wire bond
1
As-bonded
Pull Force
Mode
(gram-f)
1 (100%)
3.9 –5.5
0
5
6
7
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Wet clean and plasma clean prior to
wirebond
Oil from human skin was introduced on
bond fingers after burn-in, then wet
cleaned.
*Oil from human skin was introduced
on bond fingers after burn-in, then wet
and plasma clean prior to wirebond.
*Oil from human skin was introduced
on bond fingers prior burn-in, then wet
and plasma clean prior to wirebond.
13
2 (99%)
5.6 – 7.2
4 (1%)
6.5
2 (100%)
4.2 – 6.1
2 (100%)
5.5 – 7.6
1 (100%
4.0 – 5.8
2 (95%)
5.6 - 7.8
4 (5%)
6.6 - 7.5
0
4
HTS , 500 hrs
Pull Force
Mode
(gram-f)
1 (98%)
4.4 – 6.0
2 (97%)
5.7 – 7.3
2( 2%)
6
4 (3%)
6.5 – 7.1
1 (100%)
4.4 – 5.6
2 (97%)
5.5 – 7.3
4 ( 3%)
5.7 – 7.2)
0
1 (100%)
4.2 – 6.0
2 (100%)
5.4 – 7.4
1 (100%)
4.1 – 5.8
2 (97%)
5.5 – 7.7
4 (3%)
6.2 – 6.5
0
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Reliability Evaluation… con’t

Notes:
 Cleaning process
a. Wet – used Isopropyl Alcohol, and de-ionized (DI) water.
b. Plasma – used 100% Argon gas

Bond pull Strength test Sample size:
a. As-bonded: 50-65 wires/unit
b. Post 500 hrs HTS: 100 wires/unit

Wire bond Strength Pull modes
1 – break at neck above the ball
2 – break at wire span
4 – break at wedge bond
mode 2
mode 1
CC256
Chip Carrier
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Bond pull hook
mode 4
Au wire
LGA
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Reliability Evaluation… con’t
 The bond strength pull mode were at wire neck
above the gold ball, and at wire span.
 The absence of gold ball-to-lead finger separation indicates
good gold wire bonding to Chip Carrier’s lead finger.
 The bond strength measured on samples were
above the Mil-Std-883 TM2011 minimum
requirement.
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Summary
 Actel’s near-die size Chip Carrier is a viable
alternative for Known-good-die (KGD). It eliminate
the challenges associated with handling, testing,
and programming of today’s high I/O, high density
devices in bare die format.
 Chip Carrier can be used in both flip chip or wire
bonding format.
 A slight deposit of contamination coming from the
environment and handling during assembly and test
is expected on external bond fingers of Chip Carrier.
However, this can be controlled by implementing
good handling and cleaning procedure.
Thanks!
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