Transcript SDRAM Memory Controller  Static RAM Technology 6T Memory Cell Memory Access Timing  Dynamic RAM Technology 1T Memory Cell Memory Access Timing CS 150 - Fall.

SDRAM Memory Controller
 Static RAM Technology
6T Memory Cell
Memory Access Timing
 Dynamic RAM Technology
1T Memory Cell
Memory Access Timing
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Tri-State Gates
IN
OUT
+
OE_L
In OE_L Out
X
1
Z
0
0
0
1
0
1
IN
OUT
+
OE_L
OUT
OUT
OE_L
OE_L
IN
IN
0
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0
Slick Multiplexer Implementation
2:1 Multiplexer
S
0
1
Out
IN0
IN1
IN0
IN1
S
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OUT
Basic Memory Subsystem Block Diagram
Word Line
Address
Decoder
Memory
cell
2n word
lines
what happens
if n and/or m is
very large?
n Address
Bits
m Bit Lines
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Static RAM Cell
word
6-Transistor SRAM Cell
0
0
bit
word
(row select)
1
1
bit
 Write:
1. Drive bit lines (bit=1, bit=0)
2. Select row
bit
bit
 Read:
replaced with pullup
to save
1. Precharge bit and bit to Vdd or Vdd/2 => make
surearea
equal!
2.. Select row
3. Cell pulls one line low
4. Sense amp on column detects difference between bit and bit
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Typical SRAM Organization: 16-word x 4-bit
Din 3
Din 2
Din 1
Din 0
WrEn
Precharge
Wr Driver &
- Precharger+
Wr Driver &
- Precharger+
Wr Driver &
- Precharger+
SRAM
Cell
SRAM
Cell
SRAM
Cell
SRAM
Cell
SRAM
Cell
SRAM
Cell
SRAM
Cell
SRAM
Cell
:
:
:
:
SRAM
Cell
SRAM
Cell
SRAM
Cell
SRAM
Cell
- Sense Amp+
- Sense Amp+
- Sense Amp+
- Sense Amp+
Dout 3
Dout 2
Dout 1
Dout 0
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Word 0
Word 1
Word 15
Address Decoder
Wr Driver &
- Precharger+
A0
A1
A2
A3
Logic Diagram of a Typical SRAM
 Write Enable is usually active low
(WE_L)
 Din and Dout are combined to
save pins:
A new control signal, output enable
(OE_L) is needed
WE_L is asserted (Low), OE_L is
disasserted (High)
D serves as the data input pin
WE_L is disasserted (High), OE_L is
asserted (Low)
A
N
WE_L
OE_L
D is the data output pin
Both WE_L and OE_L are asserted:
Result is unknown. Don’t do that!!!
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2 N words
x M bit
SRAM
M
D
Typical SRAM Timing
A
N
WE_L
OE_L
2 N words
x M bit
SRAM
D
M
Write Timing:
D
OE determines direction
Hi = Write, Lo = Read
Writes are dangerous! Be careful!
Double signaling: OE Hi, WE Lo
Read Timing:
High Z
Data In
Data Out
Data Out
Junk
A
Write Address
Read Address
Read Address
OE_L
WE_L
Write
Hold Time
Write Setup Time
Read Access
Time
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Read Access
Time
Problems with SRAM
 Six transistors use up lots
of area
 Consider a “Zero” is stored
in the cell:
Transistor N1 will try to pull
“bit” to 0
Transistor P2 will try to pull
“bit bar” to 1
 Bit lines are already precharged high: Are P1 and P2
really necessary?
Select = 1
P1
P2
Off On
On
On
On Off
N1
bit = 1
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N2
bit = 0
1-Transistor Memory Cell (DRAM)
 Write:
row select
1. Drive bit line
2. Select row
 Read:
1. Precharge bit line to Vdd/2
2. Select row
3. Cell and bit line share charges
Minute voltage changes on the bit line
4. Sense (fancy sense amp)
bit
Can detect changes of ~1 million electrons
5. Write: restore the value
 Refresh
1. Just do a dummy read to every cell
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Read is really a
read followed by
a restoring write
Classical DRAM Organization (Square)
bit (data) lines
r
o
w
d
e
c
o
d
e
r
row
address
Each intersection represents
a 1-T DRAM Cell
RAM Cell
Array
Square keeps the wires short:
Power and speed advantages
Less RC, faster precharge and
discharge is faster access time!
word (row) select
Column Selector &
I/O Circuits
data
Column
Address
 Row and Column Address together:
Select 1 bit a time
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Sense Amps & I/O
11
R
O
W
D
E
C
O
D
E
R
11
Memory Array
(2,048 x 2,048)
Storage
Word Line Cell
 Square root of bits per RAS/CAS
Row selects 1 row of 2048 bits from 2048 rows
Col selects 1 bit out of 2048 bits in such a row
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Data In
Column Decoder
…
Bit Line
A0…A10
Address Buffer
4 Mbit = 22 address bits
11 row address bits
11 col address bits
D
Data Out
DRAM Logical Organization (4 Mbit)
Q
Logic Diagram of a Typical DRAM
RAS_L
A
9
CAS_L WE_L
256K x 8
DRAM
OE_L
8
D
 Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low
 Din and Dout are combined (D):
 WE_L is asserted (Low), OE_L is disasserted (High)
D serves as the data input pin
 WE_L is disasserted (High), OE_L is asserted (Low)
D is the data output pin
 Row and column addresses share the same pins (A)
 RAS_L goes low: Pins A are latched in as row address
 CAS_L goes low: Pins A are latched in as column address
 RAS/CAS edge-sensitive
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DRAM READ Timing
RAS_L
 Every DRAM access begins at:
 Assertion of the RAS_L
 2 ways to read: early or late v. CAS
CAS_L WE_L
A
256K x 8
DRAM
9
OE_L
D
8
DRAM Read Cycle Time
RAS_L
CAS_L
A
Row Address
Col Address
Junk
Row Address
Col Address
Junk
WE_L
OE_L
D
High Z
Junk
Data Out
Read Access
Time
High Z
Data Out
Output Enable
Delay
Early Read Cycle: OE_L asserted before CAS_L
Late Read Cycle: OE_L asserted after CAS_L
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Early Read Sequencing
 Assert Row Address
 Assert RAS_L
 Commence read cycle
 Meet Row Addr setup time before RAS/hold time after RAS
 Assert OE_L
 Assert Col Address
 Assert CAS_L
 Meet Col Addr setup time before CAS/hold time after CAS
 Valid Data Out after access time
 Disassert OE_L, CAS_L, RAS_L to end cycle
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Sketch of Early Read FSM
FSM Clock?
Row Address to Memory
Setup time met?
Assert RAS_L
Hold time met?
Assert OE_L, RAS_L
Col Address to Memory
Setup time met?
Assert OE_L, RAS_L, CAS_L
Hold time met?
Assert OE_L, RAS_L, CAS_L
Data Available (better grab it!)
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Late Read Sequencing
 Assert Row Address
 Assert RAS_L
 Commence read cycle
 Meet Row Addr setup time before RAS/hold time after RAS
 Assert Col Address
 Assert CAS_L
 Meet Col Addr setup time before CAS/hold time after CAS
 Assert OE_L
 Valid Data Out after access time
 Disassert OE_L, CAS_L, RAS_L to end cycle
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Sketch of Late Read FSM
FSM Clock?
Row Address to Memory
Setup time met?
Assert RAS_L
Hold time met?
Col Address to Memory
Assert RAS_L
Setup time met?
Col Address to Memory
Assert RAS_L, CAS_L
Hold time met?
Assert OE_L, RAS_L, CAS_L
Data Available (better grab it!)
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DRAM WRITE Timing
RAS_L
CAS_L WE_L
OE_L
 Every DRAM access begins at:
 The assertion of the RAS_L
 2 ways to write: early or late v. CAS
A
9
256K x 8
DRAM
8
Col Address
Junk
D
DRAM WR Cycle Time
RAS_L
CAS_L
A
Row Address
Col Address
Junk
Row Address
OE_L
WE_L
D
Junk
Data In
WR Access Time
Early Wr Cycle: WE_L asserted before CAS_L
Junk
Data In
Junk
WR Access Time
Late Wr Cycle: WE_L asserted after CAS_L
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Key DRAM Timing Parameters
 tRAC: minimum time from RAS line falling to the valid data
output.
 Quoted as the speed of a DRAM
 A fast 4Mb DRAM tRAC = 60 ns
 tRC: minimum time from the start of one row access to the start
of the next.
 tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns
 tCAC: minimum time from CAS line falling to valid data output.
 15 ns for a 4Mbit DRAM with a tRAC of 60 ns
 tPC: minimum time from the start of one column access to the
start of the next.
 35 ns for a 4Mbit DRAM with a tRAC of 60 ns
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SDRAM Memory Controller
 Static RAM Technology
6T Memory Cell
Memory Access Timing
 Dynamic RAM Technology
1T Memory Cell
Memory Access Timing
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