Transcript ECE 448 Lecture 17 ASIC vs. FPGA ECE 448 – FPGA and ASIC Design with VHDL George Mason University.

ECE 448
Lecture 17
ASIC vs. FPGA
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
FPGAs vs. ASICs
ASICs
FPGAs
Off-the-shelf
High performance
Low development costs
Low power
Short time to the market
Low cost (but only
in high volumes)
ECE 448 – FPGA and ASIC Design with VHDL
Reconfigurability
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ASIC Design Example – Factoring circuit/GMU
Global Memory
Local
Memory
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ASIC 130 nm vs. Virtex II 6000
Factoring/GMU
19.68 mm
19.80 mm
51x
Area of Xilinx Virtex II 6000
FPGA
(estimation by R.J. Lim Fong,
MS Thesis, VPI, 2004)
2.7 mm
2.82 mm
Area of an ASIC with equivalent functionality
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ASICs vs. FPGAs
Source:
I. Kuon, J. Rose,
University of Toronto
“Measuring the Gap Between
FPGAs and ASICs”
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems,
vol. 62, no. 2, Feb 2007.
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ASICs vs. FPGAs
23 representative circuits implemented using
FPGAs and ASICs
- computer arithmetic (booth, cordic18, cordic8, etc.)
- digital signal processing (rs_encoder, fir3, fir24,
etc.)
- communications (ethernet, mac1, atm, etc.)
- cryptography (des_area, des_perf, aes, aes192,
etc.)
- scientific computations (molecular, raytracer, etc.)
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Simplified ASIC Design Flow
Front-End
Design
Back-End
Design
Synthesis
Timing Analysis
Floorplanning
Placement
Clock Tree Synthesis
Routing
Design for Manufacturing
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Major ASIC Toolsets
Cadence
Magma
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ASIC Design Flow
Algorithm
Specification
RTL Design
Verilog, VHDL
Reference
Implementation
C, C++
Synopsys Design Compiler
stdcell lib
Logic Synthesis
Layout
VCS
Hercules
Calibre
die area
pin count
LVS
Mentor Calibre
Synopsys StarRCXT
Parasitic Extraction
latency
throughput
(post-synthesis)
Simulation
Synopsys IC Compiler
Cadence Encounter
process lib
Design
Quality
test vectors
VCD
Simulation
PrimeTime
latency
throughp
ut
(post
P&R)
power diss
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Systems on Chip: Microprocessor + FPGA Logic
• Xilinx Zynq (~2012)
• Zynq-7000 All Programmable
SoCs with Cortex-A9 MPCore
• Altera Arria V & Cyclone V
(~2012)
• Hard processor system (HPS)
with Cortex-A9 MPCore
• Microsemi Smartfusion
(~2010)
• Cortex M3
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Zynq - Extensible Processing Platform
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Zynq – 7000 EPP
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High-Level Synthesis
I/O
Behavior
Target
Library
Algorithm
High-Level
Synthesis
RTL
Design
Logic
Synthesis
Classic RTL
Design Flow
Gate level
Netlist
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Need for High-Level Synthesis
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Higher level of abstraction
Modeling complex designs
Reduce design efforts
Fast turnaround time
Technology independence
Ease of HW/SW partitioning
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Advantages of High-Level Synthesis
•
•
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Easy to model higher level of complexities
Smaller in size source compared to RTL code
Generates RTL much faster than manual method
Multi-cycle functionality
Loops
Memory Access
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Untimed C Domain
SystemC
(Non-implementation-specific)
Timed C Domain
RTL Domain
(Implementation-specific)
Verilog
and VHDL
(Implementation-specific)
ECE 448 – FPGA and ASIC Design with VHDL
Augmented
C/C++
More abstract, less
implementationspecific
Pure C/C++
Different Levels of C/C++ Synthesis Abstraction
Less abstract, more
implementationspecific
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 20
Pure Untimed C/C++ Design Flow
Verilog /
VHDL RTL
User interaction
and guidence
RTL
Synthesis
Gate-level
netlist
ASIC
target
Pure C/C++
Pure C/C++
Synthesis
Auto-generated,
implementation-specific
FPGA
target
- Non-implementation-specific
- Easy to create
- Fast to simulate
- Easy to modify
Verilog /
VHDL RTL
RTL
Synthesis
LUT/CLBlevel netlist
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Program Entry
Program
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Platform Mapping
SW/HW Partitioning
Program
Software
(executed in
the microprocessor
system)
ECE 448 – FPGA and ASIC Design with VHDL
Hardware
(executed in
the reconfigurable
processor
system)
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SW/HW Partitioning & Coding
Traditional Approach
Specification
SW/HW Partitioning
SW Coding
HW Coding
SW Compilation
HW Compilation
SW Profiling
HW Profiling
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SW/HW Partitioning & Coding
New Approach
Specification
SW/HW Coding
SW/HW Partitioning
SW Compilation
HW Compilation
SW Profiling
HW Profiling
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Still Predominant for Hardware Design
VHDL
& Verilog
Government
Developed
Ada based
Commercially
Developed
C based
Strongly Type Cast
Mildly Type Cast
Case-insensitive
Case-sensitive
Difficult to learn
Easier to Learn
More Powerful
Less Powerful
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How to learn Verilog by yourself ?
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How to learn Verilog by yourself ?
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Digital system design technologies
coverage in the CpE & EE programs at GMU
Microprocessors
ECE 445
ASICs
FPGAs
Computer
Organization
ECE 448
FPGA and ASIC Design with VHDL
ECE 447
Single Chip
Microcomputers
ECE 431
Digital Circuit Design
ECE 510
Real-Time
Concepts
ECE 545
Digital System
Design with VHDL
Computer
Arithmetic
ECE 511
Microprocessors
ECE 645
ECE 611
Advanced
Microprocessors
ECE 586
Digital
Integrated
Circuits
ECE 612
Real-Time Embedded
Systems
ECE 681
VLSI Design
for ASICs
ECE Department
Programs
MS in Electrical Engineering
MS EE
MS in Computer Engineering
MS CpE
BIOENGINEERING
DIGITAL SYSTEMS DESIGN
COMMUNICATIONS
& NETWORKING
MICROPROCESSORS
& EMBEDDED SYSTEMS
SIGNAL PROCESSING
DIGITAL SIGNAL PROCESSING
CONTROL & ROBOTICS
COMPUTER NETWORKS
MICROELECTRONICS/
NANOELECTRONICS
NETWORK & SYSTEM
SECURITY
SYSTEM DESIGN
Specializations
DIGITAL SYSTEMS DESIGN
Concentration advisors: Kris Gaj, Ken Hintz, Houman Homayoun
1. ECE 545 Digital System Design with VHDL
– K. Gaj, project, FPGA design with VHDL,
2. ECE 645 Computer Arithmetic
– K. Gaj, project, FPGA design with VHDL
3. ECE 681 VLSI Design for ASICs
– H. Homayoun, project/lab, front-end and back-end ASIC design with
Synopsys tools
4. ECE 586 Digital Integrated Circuits
– D. Ioannou, R. Mulpuri,
5a. ECE 682 VLSI Test Concepts
– T. Storey
5b. ECE 699 Digital Signals Processing Hardware Architectures
– A. Cohen, project, FPGA design with VHDL and Matlab/Simulink
ECE 545 Textbook
Pong P. Chu, RTL Hardware Design Using VHDL,
Wiley-Interscience, 2006.
DIGITAL SIGNAL PROCESSING
Concentration advisors: Aaron Cohen, Kris Gaj, Ken Hintz, Jill Nelson,
Kathleen Wage
1. ECE 535 Digital Signal Processing
– L. Griffiths, J. Nelson, Matlab
2. ECE 545 Digital System Design with VHDL
– K. Gaj, project, FPGA design with VHDL
3. ECE 645 Computer Arithmetic
– K. Gaj, project, FPGA design with VHDL
4. ECE 699 Digital Signals Processing Hardware Architectures
– A. Cohen, project, FPGA design with VHDL and Matlab/Simulink
5a. ECE 537 Introduction to Digital Image Processing
– K. Hintz
5b. ECE 738 Advanced Digital Signal Processing
– K. Wage
Degree Options
MS Thesis
Option
Research Project
Option
8
courses
9
courses
ECE 799
Master’s Thesis
(6 cr. hrs)
ECE 798
Research Project
Scholarly paper
Scholarly Paper
Option
10
courses
Scholarly paper
Other Resources
Xcell Journal
available for FREE on line @
http://www.xilinx.com/publications/xcellonline/
Electronic Engineering Journal
available for FREE by e-mail after subscribing @
http://www.eejournal.com/subscribe
or on the web @
http://www.eejournal.com/design/fpga
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