ESE534 Computer Organization

Day 6: February 12, 2014 Energy, Power, Reliability Penn ESE534 Spring2014 -- Mehta & DeHon 1

Today

• Energy tradeoffs • Voltage limits and leakage • Variations • [more of the gory transistor equations…] 2 Penn ESE534 Spring2014 -- Mehta & DeHon

At Issue

• Many now argue

energy

ultimate scaling limit – (not lithography, costs, …) will be the • Proliferation of portable and handheld devices – …battery size and life biggest issues • Cooling, energy costs may dominate cost of electronics – Even server room applications 3 Penn ESE534 Spring2014 -- Mehta & DeHon

Preclass 1

• 1GHz case – Voltage?

– Energy per Operation?

– Power required for 2 processors?

• 2GHz case – Voltage?

– Energy per Operation?

– Power required for 1 processor?

Penn ESE534 Spring2014 -- Mehta & DeHon 4

Preclass 1 Lesson

• What does Preclass 1 result tell us?

Penn ESE534 Spring2014 -- Mehta & DeHon 5

Energy and Delay

E

 1 2 2

CV

t gd

=Q/I=(CV)/I I

d,sat

=(

m

C

OX

/2)(W/L)(V

gs

-V

TH

)

2 6 Penn ESE534 Spring2014 -- Mehta & DeHon

Energy/Delay Tradeoff

• • E  V 2 t gd  1/V

E

 1 2

CV

t gd =(CV)/I I d,sat  (V gs -V TH ) 2 • We can trade speed for energy • E × ( t gd ) 2  constant Martin

et al.

Power-Aware Computing

, Kluwer 2001 http://caltechcstr.library.caltech.edu/308/ 7 Penn ESE534 Spring2014 -- Mehta & DeHon

Area/Time Tradeoff

• Also have Area-Time tradeoffs – HW2 spatial vs temporal multipliers – See more next week • Compensate slowdown with additional parallelism • …trade Area for Energy  Architectural Option 8 Penn ESE534 Spring2014 -- Mehta & DeHon

Question

• By how much can we reduce energy?

• What limits us?

Penn ESE534 Spring2014 -- Mehta & DeHon 9

Challenge: Power

Penn ESE534 Spring2014 -- Mehta & DeHon 10

Origin of Power Challenge

• Limited capacity to remove heat – ~100W/cm 2 – 1-10W/cm 2 force air ambient • Transistors per chip grow at Moore’s Law rate = (1/F) 2 • Energy/transistor must decrease at this rate to keep constant power density • P/tr  CV 2 f • E/tr  CV 2 – …but V scaling more slowly than F 11 Penn ESE534 Spring2014 -- Mehta & DeHon

ITRS V dd Scaling: More slowly than F Penn ESE534 Spring2014 -- Mehta & DeHon 12

ITRS CV 2 Scaling: More slowly than (1/F) 2 Penn ESE534 Spring2014 -- Mehta & DeHon 13

Origin of Power Challenge

• Transistors per chip grow at Moore’s Law rate = (1/F) 2 • Energy/transistor must decrease at this rate to keep constant • E/tr  CV 2 Penn ESE534 Spring2014 -- Mehta & DeHon 14

Historical Power Scaling

[Horowitz et al. / IEDM 2005] Penn ESE534 Spring2014 -- Mehta & DeHon 15

Microprocessor Power Density

Watts The Future of Computing Performance: Game Over or Next Level?

National Academy Press, 2011 16

Intel Power Density

Penn ESE534 Spring2014 -- Mehta & DeHon 17

Impact

Power Limits Integration Density Limit Constant Power Limit 45nm 32nm 22nm 16nm 11nm

Source: Carter/Intel Penn ESE534 Spring2014 -- Mehta & DeHon 18 18

Impact

• Power density is limiting scaling – Can already place more transistors on a chip than we can afford to turn on!

• Power is potential challenge/limiter for all future chips.

– Only turn on small percentage of transistors?

– Operate those transistors as much slower frequency?

– Find a way to drop V dd ?

19 Penn ESE534 Spring2014 -- Mehta & DeHon

How far can we reduce V

dd

?

20 Penn ESE534 Spring2014 -- Mehta & DeHon

Limits

• Ability to turn off the transistor • Parameter Variations • Noise (not covered today) Penn ESE534 Spring2014 -- Mehta & DeHon 21

MOSFET Conduction

From: http://en.wikipedia.org/wiki/File:IvsV_mosfet.png

Penn ESE534 Spring2014 -- Mehta & DeHon 22

Transistor Conduction

• Three regions – Subthreshold (V gs V TH ) and (V ds < (V gs -V TH )) – Saturation (V gs >V TH ) and (V ds > (V gs -V TH )) 23 Penn ESE534 Spring2014 -- Mehta & DeHon

Saturation Region

• (V gs >V TH ) • (V ds > (V gs -V TH ))

I

ds,sat

=(

m

C

OX

/2)(W/L)(V

gs

-V

TH

)

2 24 Penn ESE534 Spring2014 -- Mehta & DeHon

Linear Region

• (V gs >V TH ) • (V ds < (V gs -V TH )) I ds,lin =( m C OX )(W/L)((V gs -V TH )V ds -(V ds ) 2 /2) 25 Penn ESE534 Spring2014 -- Mehta & DeHon

Subthreshold Region

• (V gs

I I

 Penn ESE534 Spring2014 -- Mehta & DeHon  [Frank, IBM J. R&D v46n2/3p235] 26

Operating a Transistor

• Concerned about I on and I off • I on drive (saturation) current for charging – Determines speed: T gd = CV/I • I off leakage current – Determines leakage power/energy: • P • E leak leak = V × I leak = V × I leak × T cycle 27 Penn ESE534 Spring2014 -- Mehta & DeHon

Leakage

• To avoid leakage want I off • Switch V from V dd to 0 very small • V gs in off state is 0 (V gs

I



I

   10 28 Penn ESE534 Spring2014 -- Mehta & DeHon  

Leakage

I

 10  • S  90mV for single gate • S  70mV for double gate • For lowest leakage, want S small, V TH large • 4 orders of magnitude I VT /I off  V TH >280mV Leakage limits V TH Penn ESE534 Spring2014 -- Mehta & DeHon in turn limits V dd 29

How maximize I

on

/I

off

?

• Maximize I on /I off – for given V dd • Get to pick V TH , V dd ? E sw  CV 2

I

d,sat

=(

m

C

OX

/2)(W/L)(V

gs

-V

TH

)

2 I d,lin =( m C OX )(W/L)(V gs -V TH )V ds -(V ds ) 2 /2

I I

  30 Penn ESE534 Spring2014 -- Mehta & DeHon 

Preclass 2

• E = E sw + E leak • E leak = V × I leak × T cycle • E sw  CV 2

I I

• I chip-leak = N devices × I tr-leak   31

• E leak (V) ?

• T cycle (V)?

Preclass 2

Penn ESE534 Spring2014 -- Mehta & DeHon 32

In Class

• Assign calculations – SIMD – each student computes for a different Voltage • Collect results on board • Group: Identify minimum energy point and discuss 33 Penn ESE534 Spring2014 -- Mehta & DeHon

Graph for In Class

Penn ESE534 Spring2014 -- Mehta & DeHon 35

Impact

• Subthreshold slope prevents us from scaling voltage down arbitrarily.

• Induces a minimum operating energy.

36 Penn ESE534 Spring2014 -- Mehta & DeHon

Challenge: Variation

Penn ESE534 Spring2014 -- Mehta & DeHon 37

Statistical Dopant Count and Placement Penn ESE534 Spring2014 -- Mehta & DeHon 38 [Bernstein et al, IBM JRD 2006]

V

th

Variability @ 65nm

Penn ESE534 Spring2014 -- Mehta & DeHon 39 [Bernstein et al, IBM JRD 2006]

Variation

• Fewer dopants, atoms  increasing Variation • How do we deal with variation?

% variation in V TH (From ITRS prediction) 40 40 Penn ESE534 Spring2014 -- Mehta & DeHon

Impact of Variation?

• Higher V TH ?

– Not drive as strongly  – I d,sat  (V gs -V TH ) 2 slower • Lower V TH ?

– Not turn off as well 

I

 leaks more 10 41 Penn ESE534 Spring2014 -- Mehta & DeHon 

Variation

• Margin for expected variation • Must assume V TH can be any value in range I on,min =I on ( Vth,max ) I d,sat  (V gs -V TH ) 2 V gs = V dd V TH Penn ESE534 Spring2014 -- Mehta & DeHon 42

Margining

• Must raise V dd to increase drive strength • Increase energy I on,min =I on ( Vth,max ) I d,sat  (V gs -V TH ) 2 V gs = V dd V TH Penn ESE534 Spring2014 -- Mehta & DeHon 43

Variation

• Increasing variation forces higher voltages – On top of our leakage limits Penn ESE534 Spring2014 -- Mehta & DeHon 44 44

Old

Variations

New

• Margins growing due to increasing variation Delay • Margined value may be worse than older technology?

45 Penn ESE534 Spring2014 -- Mehta & DeHon

End of Energy Scaling?

Black nominal Grey with variation [Bol

et al

., IEEE TR VLSI Sys 17(10):1508 —1519] Penn ESE534 Spring2014 -- Mehta & DeHon 46

Chips Growing

• Larger chips (billions of transistors)  sample further out on distribution curve From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg

47 Penn ESE534 Spring2014 -- Mehta & DeHon

Big Ideas

• Can trade time for energy – … area for energy • Variation and leakage limit voltage scaling • Power major limiter going forward – Can put more transistors on a chip than can switch • Continued scaling demands – Deal with noisier components • High variation • … other noise sources 48 Penn ESE534 Spring2014 -- Mehta & DeHon

Admin

• Homework 2 due Tonight • Reading for Monday on web • Homework 3 due next Wednesday Penn ESE534 Spring2014 -- Mehta & DeHon 49