Transcript Developed by You 3D Optimization for Intel® Graphics, Gen9 Andrew Lauritzen - Graphics Software Engineer, Intel Corporation Michael Apodaca - Principal Engineer,

Developed by You
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3D Optimization for Intel® Graphics, Gen9
Andrew Lauritzen - Graphics Software Engineer, Intel Corporation
Michael Apodaca - Principal Engineer, Intel Corporation
GVCS004
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Agenda
• Graphics API Overhead
• Commands and State
• Resource Binding
• New GPU Features
• Summary and Q&A
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Graphics API Overhead
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Graphics API Overhead
• Most GPU vendors have complex drivers
- Do lots of fancy optimizations on the fly
- Costs CPU cycles, but makes the GPU run faster
• Drivers spawn threads that conflict with application
- Driver thread often consumes an entire core by itself
- Plus another core for the game submission thread
- Minimal multithreading beyond these two threads
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CPU/GPU Optimization Trade-off
• Has recently become far more serious with SoCs
- Even if not “CPU bound”, CPU/GPU share power
- More CPU load => less GPU power/performance
• Complex CPU optimizations are not a good idea…
- Tax on all applications, even well-optimized ones
- CPU work can take more power than it saves on the GPU!
- Leads to lower overall performance
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Thinner Intel® Graphics Driver
• To address this, Intel wrote a much thinner DirectX* 11 driver
• Big benefit to well-written applications
- But does far less work to make poor ones run well
- i.e. no redundant state elimination, minimal state-based shader compiles, etc.
• Still unavoidable CPU overhead due to API design
- New APIs – DirectX 12, Vulkan, Metal - address this
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High Efficiency Graphics APIs
• Large increase in power efficiency
- Power saved on the CPU can be given to the GPU
- Applications can both run faster and use less power
• Additional GPU optimization opportunities
- i.e. stuff that we had to drop in the thinner driver
- Pipeline state objects give the driver more context
• This presentation will primarily use examples from DirectX* 12
- In most cases similar concepts apply to Vulkan and Metal
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Power and Performance
DirectX* 11
DirectX 12
Less power @ same performance
DirectX 11
DirectX 12
More performance @ same power
DirectX 12 can significantly reduce CPU power or improve performance
Source: https://software.intel.com/en-us/blogs/2014/08/11/siggraph-2014-directx-12-on-intel
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Commands and State
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State in DirectX* 11
•
DirectX*
11 context is “stateful”
- State grouped into moderately sized chunks
(Immutable State Objects)
- e.g., RasterState, DepthStencilState, BlendState,
etc.
• Groupings do not always map perfectly to
hardware
- i.e., D3D BlendState != GPU BlendState
- Also, driver must still validate state combinations
and may perform GPU optimizations by
combining multiple D3D state objects at Draw
time
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Input Assembler
Vertex Shader
Hull Shader
Domain Shader
Geometry Shader
Raster State
Pixel Shader
Blend State
Depth Stencil State
State in DirectX* 12
• Immutable, monolithic Pipeline State Objects
(PSOs)
- Single object captures as much state as possible
- Much lower chance of missing driver context
- Allows state validation and optimizations to occur
at load time
- Allows more advanced link-time optimizations on
shaders
Pipeline State
Input Assembler
Vertex Shader
Hull Shader
Domain Shader
Geometry Shader
Raster State
Pixel Shader
Blend State
Depth Stencil State
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Pipeline State Objects (PSO)
• Create PSOs at initialization time
- Multithread your initialization/PSO creation code!
- Use PSO “libraries”/caching
 Compress (LZMA or similar) many PSOs together before storing
 Often a lot of redundancy that can be compressed out
• Drivers will optimize PSO transitions
- e.g., Culling redundant GPU states
- Doesn’t eliminate the need to sort to reduce state changes
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DirectX* 11 Deferred Contexts
• Limited parallelism with a single context
• Deferred contexts do not address the problems:
- CPU performance and cache issues with transient objects
- State mismatch and lazy state setting
- Inherited internal states
- MAP_DISCARD renaming, hazard tracking, etc.
- Non-trivial patching happens at submission time
• Result: more overhead and limited parallelism
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DirectX* 12 Direct Command Lists
• Transient / Single-Use Command Lists
CommandList
• No state inheritance between Direct Command Lists
- No API state or internal state inheritance (renaming, etc.)
• Resource management
- No implicit resource renaming
- Explicit barriers to handle hazards and resource transitions
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CommandList
DirectX* 12 Bundles
• Persistent / Re-executable Command Lists
CommandList
• Some minimal state inheritance is allowed
- Some driver patching may occur at Execute time
- If you don’t need to inherit something, set it (again) in the
bundle
Bundle
Bundle
CommandList
• Note: Overhead is already very low in DirectX* 12
- Usually need ~10+ draws to make bundles a win
- Don’t add any GPU overhead/indirections to enable
bundles!
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CommandList
DirectX* 12 Command List Allocators
• Container for GPU Command Buffer et al. allocations
• Complexity:
- Can only be accessed by a single thread; use ~1 allocator per thread
- Reset is optimized for reusing with similarly sized Command Lists; therefore
should be associated with same/similar Command Lists
- Application doesn’t know the actual memory size
 Memory size ∝ Number of Draw calls
• Recommendation:
- Use a single allocator for multiple ‘small’ Command Lists
- Use a single allocator for a single ‘large’ Command List
- Reuse accordingly
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DirectX* 12 Command Queues
• Exposes GPU Parallelism
- Multi-Engine and Multi-GPU
• 3D and Compute are not simultaneous
- Queues may pre-empt each other
• Copy might be simultaneous with 3D and Compute
- Driver will make decision based on GPU performance and capabilities
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DirectX* 12 Execute Indirect
• Expands on Indirect Draw/Dispatch
• Command signature defines indirect
argument buffer format
• Indirect arguments can contain
- Draw/dispatch parameters
- Resource bindings
• Optional count buffer
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IB
VB
Draw
UAV
CBV
Draw
IB Args
VB Args
Draw Args
UAV Args
CBV Args
Draw Args
IB Args
VB Args
Draw Args
UAV Args
CBV Args
Draw Args
Execute Indirect on Gen9
• Must be executed on GPU
• Internal Compute Shader patches
Command List buffer
• Optimize transition barriers on
Argument / Count buffers
• DirectX* 11 DrawIndirect:
- Count = 1
- No resource bindings
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Resource Binding
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Resource Descriptors
• Resources views are effectively just a small structure
- Metadata and a pointer to memory (usually ~32-64 bytes)
- Stuff like texture dimensions, format, layout, etc.
• Direct3D* 12 directly exposes these “descriptors”
- Independent from the actual memory they reference
- Can be created/copied/etc. freely
- Application must ensure no dangling pointers
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Resource Descriptors
• Not an API object – manipulated directly by application
- Descriptor size query-able by application
- Can be created at any time; free-threaded API call
• Descriptors are put into “heaps” (arrays)
- Constant buffer (CBV), shader resource (SRV) and unordered access (UAV)
views can be mixed in one heap
- Samplers in a separate heap
• Changing heaps is expensive (pipeline flush)
- Ideally use a single heap of each type (sampler, CBV/SRV/UAV)
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Descriptors Example
Descriptor Heap
D3D12_UNORDERED_ACCESS_VIEW_DESC uavDesc = { ... };
device->CreateUnorderedAccessView(res, desc, [uavHandle])
D3D12_CONSTANT_BUFFER_VIEW_DESC cbvDesc = { ... };
device->CreateConstantBufferView(res, cbvDesc, [cbvHandle]);
UAV
CBV
...
SRV
CBV
SRV
SRV
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Root Signature
• Think of it like a function signature for your shader(s)
• Defines parameters and how they map to shader inputs
- Root constants (data: zero indirections)
- Root descriptors (pointer to data: one indirection)
- Descriptor tables (pointer to descriptors: two indirections)
• Each parameter can be visible to one or more shader stages
• Parameters are “versioned” by implementation/hardware
- This is the single place the “stream” of versions are managed
- Maximum size is very small to avoid abuse
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Root Parameter Indirections
Root Signature
0
Root Constants
1
Root Descriptor
2
Descriptor Table
Memory
Descriptor Heap
…
UAV
CBV
…
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Root Constants
• Pass a small number of constants directly to shaders
- Bound to shader as a single constant buffer
• Useful for simple indirections; draw ID, material ID, etc.
- Avoids creating versioned memory, descriptor, heap, etc.
- Shader can use to look up into arbitrary data structures
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Root Descriptors
• Stores a single descriptor directly as a root parameter
- No need to burn through descriptor heap space
- Most useful for a descriptor that changes ~ every draw
• Can only reference “raw data”
- Only buffer resources (CBVs, SRVs/UAVs of buffers)
- No type conversions (i.e., only float/uint/sint components)
- No out of bounds checking
- i.e. it’s just a pointer to memory
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Descriptor Tables
• Maps continuous range of descriptors to shader slots
- Can mix SRVs, UAVs, and CBVs arbitrarily
- Multiple descriptor tables can point to disjoint ranges
• Example: Use separate parameters for different update frequencies
- Per-scene, per-material, per-instance, per-draw, etc.
- Similar to constant buffers, now also for the descriptors too
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Root Signature Example
0
Descriptor Table
t1
b1
1
Descriptor Table
u0
b2
t4
t5
D3D12_DESCRIPTOR_RANGE Param0Ranges[3];
Param0Ranges[0].Init(D3D12_DESCRIPTOR_RANGE_SRV, 1, 1); // t1
Param0Ranges[1].Init(D3D12_DESCRIPTOR_RANGE_CBV, 1, 1); // b1
Param0Ranges[2].Init(D3D12_DESCRIPTOR_RANGE_SRV, 2, 4); // t4-t5
D3D12_DESCRIPTOR_RANGE Param1Ranges[2];
Param1Ranges[0].Init(D3D12_DESCRIPTOR_RANGE_UAV, 1, 0); // u0
Param1Ranges[1].Init(D3D12_DESCRIPTOR_RANGE_CBV, 1, 2); // b2
// Visibility to all stages allows sharing binding tables
D3D12_ROOT_PARAMETER Param[2];
Param[0].InitAsDescriptorTable(3, Param0Ranges, D3D12_SHADER_VISIBILITY_ALL);
Param[1].InitAsDescriptorTable(2, Param1Ranges, D3D12_SHADER_VISIBILITY_ALL);
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Root Signature Example
0
Descriptor Table
t1
b1
1
Descriptor Table
u0
b2
2
Shader Resource View
t0
3
uint4 Constant
b0
t4
t5
...
Param[2].InitAsShaderResourceView(1, 0); // t0
Param[3].InitAsConstants(4, 0); // b0 (4x32-bit constants)
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Root Signature Example (HLSL)
0
Descriptor Table
t1
b1
1
Descriptor Table
u0
b2
2
Shader Resource View
t0
3
uint4 Constant
b0
t4
t5
DescriptorTable(SRV(t1), CBV(b1), SRV(t4, numDescriptors=2)),
DescriptorTable(UAV(u0), CBV(b2)),
SRV(t0),
RootConstants(b0, num32BitConstants=4)
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Binding Example
Descriptor Heap
Root Signature
0
Descriptor Table
t1
b1
1
Descriptor Table
u0
b2
2
Shader Resource View
t0
3
uint4 Constant
b0
t4
t5
UAV
CBV
SRV
cmdList->SetGraphicsRootDescriptorTable(0, [srvGPUHandle]);
cmdList->SetGraphicsRootDescriptorTable(1, [uavGPUHandle]);
CBV
cmdList->SetGraphicsRootConstantBufferView(2, [srvCPUHandle]);
SRV
cmdList->SetGraphicsRoot32BitConstants(3, {1,3,3,7}, 0, 4);
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SRV
Binding Example
Descriptor Heap
Root Signature
0
Descriptor Table
t1
b1
1
Descriptor Table
u0
b2
2
Shader Resource View
t0
SRV
3
uint4 Constant
b0
1, 3, 3, 7
t4
t5
UAV
CBV
SRV
cmdList->SetGraphicsRootDescriptorTable(0, [srvGPUHandle]);
cmdList->SetGraphicsRootDescriptorTable(1, [uavGPUHandle]);
CBV
cmdList->SetGraphicsRootConstantBufferView(2, [srvCPUHandle]);
SRV
cmdList->SetGraphicsRoot32BitConstants(3, {1,3,3,7}, 0, 4);
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SRV
Resource Binding
• Root parameters map very directly to GPU implementation
- Each draw/dispatch gets a versioned copy of the root parameters
- Each root parameter gets passed to the shader register file via “push constants”
- When execution unit (EU) thread launches, values are immediately available
• Performance is very predictable
- If you change any root parameter for a given shader stage, there’s a small cost
 i.e. a new version of the draw constants are created
- Beyond that, low sensitivity to #/type of root parameters or # changed
- Unlike previous architectures, no cost for “unused” descriptors, etc.
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Descriptor Tables
• All descriptors are referenced via the “bindless resources” path
- i.e. the entire heap is indexed directly by the shader
• Setting a descriptor tables is syntactic sugar
- Driver passes the offset in the heap as a constant (DWORD)
- Shader adds the offset to the binding index in the shader
• Recommend applications switch to bindless style
- Use a single descriptor table that maps the entire heap
- Store binding indices with other material constants (cbuffers, root constants)
- Enables new capabilities: all resources are accessible without CPU intervention
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Binding Example
Root Signature
Draw Constants
0
Descriptor Table
5
1
Descriptor Table
1
2
Shader Resource View
[64-bit SRV address]
3
uint4 Constant
1, 3, 3, 7
Descriptor Heap
UAV
CBV
SRV
cmdList->SetGraphicsRootDescriptorTable(0, [srvGPUHandle]);
cmdList->SetGraphicsRootDescriptorTable(1, [uavGPUHandle]);
CBV
cmdList->SetGraphicsRootConstantBufferView(2, [srvCPUHandle]);
SRV
cmdList->SetGraphicsRoot32BitConstants(3, {1,3,3,7}, 0, 4);
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SRV
Static Samplers
• Define sampler parameters right in the root signature
- Or right in the shader with HLSL root signature language
• If only static samplers are used then it isn’t necessary to manage a
sampler heap anymore!
• No GPU performance disadvantage
- Driver places static samplers in the regular sampler heap
- Same as application putting them there (doesn’t count against DirectX* 12
limits)
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New GPU Features
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Conservative Rasterization
• New hardware rasterizer mode
- Includes any pixels that are at least partially covered (outer conservative)
- New pixel shader input indicates fully covered pixels (inner conservative)
• Truly conservative implementation
- No pixels missed or incorrectly flagged as fully covered
- Degenerate triangles are not culled
- Accounts for fixed point snapping error
• Many use cases in the literature
- Voxelization, uniform grids, binning, tiled rendering, anti-aliasing, shadows,
occlusion culling, texture atlases and light maps, …
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Conservative Rasterization
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Raster Ordered Views
• Aka. Pixel synchronization1
- Introduced Intel® Graphics Technology, Gen7.5 (4th generation processors)
- Now standardized in DirectX* 11.3 and 12
• Enables ordered per-pixel read/write memory accesses
- Efficiently construct deterministic (render order) per-pixel data structures
• Many applications, and fits well with conservative rasterization
- Order independent transparency, volumetric shadow maps, K-buffers,
voxelization, anti-aliasing, etc.
1 http://advances.realtimerendering.com/s2013/2013-07-23-SIGGRAPH-PixelSync.pdf
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Render Target Read
• Shader read/modify/write of the bound render targets
- Similar to raster ordered views, but through regular raster paths
- i.e. includes format conversions, hits the raster caches, etc.
• Particularly suitable for programmable blending
- Example: decals with deferred shading
- No need to move to general memory accesses and raster order views
- Format conversions are automatic and efficient
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Tiled Resources
• Sparse 2D and 3D textures
- Mega-textures
- Sparse shadow maps
- Sparse voxel octrees (coarse-grained)
• Sparse buffers
- Geometry streaming
• Efficiently add/remove high detail mips
- Respond to memory pressure
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Standard Swizzle
• Standard pixel swizzle pattern inside a 64KB tile
• Enables directly mapping textures in hardware format
- Stream textures from disk with no format conversions
- Poke portions of textures directly from CPU
• Efficient multi-adaptor sharing
- Shared textures between GPUs from different vendors
- … without several extra copies to go through linear/row-major intermediary
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Other New GPU Features
• Adaptive scalable texture compression (ASTC)
• 16x multi-sample anti-aliasing (MSAA)
• Post depth test coverage mask
• Floating point atomics (min/max/cmpexch)
• Min/max texture filtering
• Multi-plane overlays
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Summary and Q&A
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Summary and Next Steps
• High efficiency graphics APIs are a great fit for Intel hardware
- Increased performance and predictability
- Increased power efficiency
• DirectX* 12 is already supported today
- Many new GPU features are exposed
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Additional Sources of Information
• A PDF of this presentation is available from our Technical Session
Catalog: www.intel.com/idfsessionsSF. This URL is also printed on the
top of Session Agenda Pages in the Pocket Guide.
• Follow @IntelSoftware and @DirectX12
• https://software.intel.com/en-us/gamedev
• http://blogs.msdn.com/directx
• Working on DirectX* 12 on Intel?
- [email protected], @AndrewLauritzen
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Other Technical Graphics Sessions





Session
ID
Title
Time
Room
SPCS003
Technology Insight: Next Generation Intel® Processor Graphics
Architecture, Code Name Skylake
Tues
1:15 – 2:15
Level 3
Room 3016
GVCS001
Power Optimization in Intel® Graphics Technology, Gen9
Wed
9:30 – 10:30
Level 2
Room 2008
GVCS002
Enhancing 4K Media Experience in Power Optimized Intel®
Graphics, Gen9
Wed
11:00 – 12:00
Level 2
Room 2008
GVCS003
Display Stack Power Optimizations for Intel® Graphics, Gen9
Wed
5:15 – 6:15
Level 2
Room 2007
GVCS004
3D Optimizations for Intel® Graphics Technology, Gen9
Thurs
9:30 – 10:30
Level 2
Room 2007
GVCS005
Virtualized and Remote Intel® Processor Graphics for Your Data
Center
Thurs
10:45 – 11:45
Level 2
Room 2007
GVCS006
Scaling Energy Efficient Media Performance on Intel® Processor
Graphics
Thurs
1:00 – 2:00
Level 2
Room 2007
 = DONE
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Additional Sources of Information
A PDF of this presentation is available from our
Technical Session Catalog: www.intel.com/idfsessionsSF.
Additional Online information:
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Intel Processor Graphics: Architecture Whitepapers & Developer Guides
The New Intel® Microarchitecture
About Intel® Processor Graphics Technology
Open source Linux documentation of Gen Graphics and Compute Architecture
Intel® OpenCL™ SDK
Intel® 64 and IA-32 Architectures Software Developers Manual
Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient
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- http://ark.intel.com/
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