2001 ISCS Conference, October, Tokyo High speed InP-based heterojunction bipolar transistors Mark Rodwell University of California, Santa Barbara [email protected] 805-893-3244, 805-893-3262 fax.
Download ReportTranscript 2001 ISCS Conference, October, Tokyo High speed InP-based heterojunction bipolar transistors Mark Rodwell University of California, Santa Barbara [email protected] 805-893-3244, 805-893-3262 fax.
2001 ISCS Conference, October, Tokyo High speed InP-based heterojunction bipolar transistors Mark Rodwell University of California, Santa Barbara [email protected] 805-893-3244, 805-893-3262 fax How to Improve the Bandwidth of Bipolar Transistors ? kT 1 kT base collector C je Cbc Rex Rcoll 2f qIE qIE Thinner base, thinner collector higher f , but higher Rbb, Ccb what parameters are really important in HBTs ? how do we improve HBT performance ? HBT scaling: transit times 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, WE WEB LE emitter base x reduce Tb by 2:1 b improved 2:1 reduce Tc by 2:1 c improved 2:1 note that Ccb has been doubled ..we had wanted it 2:1 smaller base collector WC WBC b Tb2 / 2Dn b Tc / 2vsat AssumeWC ~ WE 's HBT scaling: lithographic dimensions 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, Rbb Rgap Rspread Rcontact Base Resistance Rbb must remain constant Le must remain ~ constant Rcontact sheet c ,vertical 2 LE Ccb/Area has been doubled ..we had wanted it 2:1 smaller …must make area=LeWe 4:1 smaller must make We & Wc 4:1 smaller WE WEB LE emitter base x reduce collector width 4:1 reduce emitter width 4:1 keep emitter length constant 's base collector WC WBC AssumeWC ~ WE HBT scaling: emitter resistivity, current density 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, 's Emitter Resistance Rex must remain constant but emitter area=LeWe is 4:1 smaller resistance per unit area must be 4:1 smaller AssumeWC ~ WE Collector current must remain constant but emitter area=LeWe is 4:1 smaller and collector area=LcWc is 4:1 smaller current density must be 4:1 larger WE WEB LE emitter base increase current density 4:1 reduce emitter resistivity 4:1 x base collector WC WBC base contact pad Scaling Laws for fast HBTs transferred-substrate for x 2 improvement of all parasitics: ft, fmax, logic speed… base 2: 1 thinner collector 2:1 thinner emitter, collector junctions 4:1 narrower current density 4:1 higher emitter Ohmic 4:1 less resistive undercut-collector emitter Challenges with Scaling: Collector mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length sets minimum size for collector Emitter Ohmic: hard to improve…how ? Current Density: dissipation, reliability Loss of breakdown avalanche Vbr never less than collector Egap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power base contact InGaAs collector undercut collector junction collector -base junction InGaAs base InP collector collector contact InGaAs subcollector InP subcollector SI substrate collector contact Narrow-mesa with 1E20 carbon-doped base emitter base contact base contact base polymer polymer sub collector SI substrate UCSB Transferred-Substrate HBT Process Flow ONR Ultra-high fmax Transferred-Substrate HBTs Michelle Lee • Substrate transfer provides access to both sides of device epitaxy • Permits simultaneous scaling of emitter and collector widths • Maximum frequency of oscillation f max f / 8RbbCcb • Sub-micron scaling of emitter and collector widths has resulted in record values of extrapolated fmax • New 140-220 GHz Vector Network Analyzer (VNA) extends device measurement range Mason's gain, U 3000 Å collector 400 Å base with 52 meV grading AlInAs / GaInAs / GaInAs HBT 25 Gains, dB • Extrapolation begins where measurements end 30 20 MSG 15 H21 10 5 Emitter, 0.4 x 6 mm2 Collector, 0.7 x 6 mm2 fmax = 1.1 THz ?? f = 204 GHz Ic = 6 mA, Vce = 1.2 V 0 10 100 Frequency, GHz 1000 220 GHz On-Wafer Network Analysis Miguel Urteaga 140-220 GHz network analysis HP8510C network analyzer & Oleson Microwave Lab frequency Extenders GGB waveguide-coupled probes 75-100 GHz network analysis GGB waveguide-coupled probes HP W-band test set 1-50 GHz network analysis GGB coax-connectorized probes HP 0.045-50 GHz test set Accurate Transistor Measurements Are Not Easy • Submicron HBTs have very low Ccb (< 5 fF) • HBT S12 is very small 230 mm 230 mm • Standard 12-term VNA calibrations do not correct S12 background error due to probe-to-probe coupling Solution Embed transistors in sufficient length of transmission line to reduce coupling Transistor in Embedded in LRL Test Structure Place calibration reference planes at transistor terminals Line-Reflect-Line Calibration Standards easily realized on-wafer Does not require accurate characterization of reflect standards Characteristics of Line Standards are well controlled in transferred-substrate microstrip wiring environment Corrupted 75-110 GHz measurements due to excessive probe-to-probe coupling Can we trust the calibration ? Miguel Urteaga 75-110 GHz calibration looks Great 140-220 GHz calibration looks OK S11 of open About 0.1 dB / 3o error S11 of through About –40 dB S11 of short S11 of through S11 of open freq (75.00GHz to 110.0GHz) freq (140.0GHz to 220.0GHz) 0.30 Probe-Probe coupling is better than –45 dB -40 -45 0.25 S21 of through line is off by less than 0.05 dB 0.20 0.15 0.10 -50 0.05 -55 0.00 -60 -0.05 -0.10 -65 -0.15 -70 140 75 80 85 90 95 freq, GHz 100 105 150 160 170 180 110 freq, GHz 190 200 210 220 Submicron transferred-substrate HBTs 0.25 mm emitter-base junction 0.4 mm Schottky collector Submicron InAlAs/InGaAs HBTs: Unbounded (?!?) Unilateral power gain 45-170 GHz 40 unbounded U 35 30 U emitter RF Gains 25 20 15 MAG/MSG h21 10 5 0 -5 1E10 1E11 Freq. Emitter: 0.3 x 18 mm2, Collector: 0.7 x 18.6 mm2 Ic = 5 mA, Vce = 1.1 V Gains are high at 200 GHz but fmax can’t be determined 1E12 collector UCSB ONR Miguel Urteaga Negative Unilateral Power Gain ??? Can U be Negative? YES, if denominator is negative This may occur for device with a negative output conductance (G22) or some positive feedback (G12) U Y21 Y12 2 4G11G 22 G 21G12 What Does Negative U Mean? Device with negative U will have infinite Unilateral Power Gain with the addition of a proper source or load impedance 2-port Network AFTER Unilateralization • Network would have negative output resistance • Can support one-port oscillation • Can provide infinite two-port power gain U Y21 Y12 GL 2 4G11 G 22 G L G 21G12 Select GL such that denominator is zero: U Simple Hybrid- HBT model will NOT show negative U Ccb Cancellation by Collector Space-Charge Vcb Moll & Camnitz, Betser and Ritter Qbase A I cTc Vcb Tc Vcb 2vsat Ccb A Ic c Tc Vcb collector space-charge layer measured 0.64 fF decrease Ccb total Collector space charge screens field, Increasing voltage decreases velocity, modulates collector space-charge offsets modulation of base charge Ccb is reduced UCSB 175 GHz Single-Stage Amplifier Miguel Urteaga Submicron HBT Program 10 S21 S11 S22 50 0.2pF 5 80 1.2ps 30 0.2ps 80 1.2ps 50 30 1.2ps 0 50 0.6ps dB IN OUT -5 -10 -15 -20 140 150 160 170 180 190 200 Freq. (GHz) 6.3 dB gain at 175 GHz 210 220 295 GHz f, & fmax HBT 2000 Å collector 300 Å base with 52 meV grading AlInAs / GaInAs / GaInAs HBT 50 h 21 Gains (dB) 40 30 U 20 V 10 f 2 CE = 1 V, J = 1.5 mA/um = 295 GHz C f MAX = 295 GHz Emitter 1 x 8 mm2, Collector 2 x 8.5 mm2. 0 1 10 Frequency (GHz) 10 2 UCSB Yoram Betser UCSB Fast InP DHBTs pk Sundararajan M Dahlstrom I - V characteristics c 20 3 kÅ collector, 400 Å base 8 15 I in steps B 7 1x 8 micron emitter, 2x 10 micron collector 10 m2 freq=165.0GHz dB(short..S(2,1))=0.000 5 of 20 uA 6 5 I (mA) m2 m1 0 4 c dB(short..S(2,1)) U dB(h21) ce -5 m1 freq=303.0GHz dB(short..S(2,1))=0.000 -10 f = 165 GHz; fmax = 303 GHz -15 3 5 V breakdown at 105 A/cm2 2 >9 V at 2*104 A/cm2 1 0 -20 1E9 1E10 1E11 0 1E12 1 2 3 V (volts) freq, Hz 4 5 6 ce 20 2 kÅ collector, 400 Å base Jc - Vce characteristics 15 5 10 4 8 10 5 Jc (A/cm ) m1 2 dB(short..S(2,1)) U dB(h21) 1 10 1x 8 micron emitter, 2x 10 micron collector 0 -5 m1 freq=216.0GHz dB(short..S(2,1))=-1.086E-10 f = 216 GHz; fmax = 210 GHz -10 -15 1E10 1E11 freq, Hz 4 V breakdown at 105 A/cm2 4 4 10 >6 V at 2*104 A/cm2 4 2 10 -20 1E9 6 104 1E12 0 0 1 2 3 V (volts) ce 4 5 UCSB InGaAs/InP DHBT, 3000 Å InP collector Sangmin Lee 2 40 I step = 20 mA fmax = 425 GHz, ft = 139 GHz b Gains (dB) 1 C I (mA) 30 BVCEO = 8 V at JE =5*104 A/cm2 U 20 h21 10 0 0 0 2 4 VCE (V) 6 8 1 10 100 Frequency (GHz) 0.5 mm x 8 mm emitter (mask) 0.4 mm x 7.5 mm emitter (junction) 1.2 mm x 8.75 mm collector Ic=4.5 mA, Vce=1.9 V Is low DHBT f due to base-collector grade ? 480 Å grade 100 Å grade collector velocity and grade: InP has higher Gamma-L separation than InGaAs → Vsat should be higher in InP → ft should be higher, not lower slow transport in InAlAs ? → thin grade ! Narrow-Mesa HBTs: high fmax if high base doping 0.5 mm emitter, 0.25 mm base contacts InP/InGaAs/InP Metamorphic DHBT on GaAs substrate Growth: 400 Å base, 2000 Å collector GaAs substrate InP metamorphic buffer layer (high thermal conductivity) Processing conventional mesa HBT narrow 2 um base mesa Results 165 GHz ft, 92 GHz fmax, 6 Volt BVCEO, b=27 UCSB triple-mesa device (not transferred-substrate) 165 GHz ft 92 GHz fmax High Speed Amplifiers 18 dB, DC--50+ GHz 20 S21 15 >397 GHz gain x bandwidth from 2 HBTs 10 5 0 S11 -5 -10 S22 -15 -20 0 10 20 30 40 50 8.2 dB, DC-80 GHz 10 Gains, dB S 21 5 0 S -5 11 -10 S 22 -15 0 10 20 30 40 50 Frequency, GHz 60 70 80 UCSB Dino Mensa PK Sundararajan HBT distributed amplifier AFOSR 11 dB, DC-87 GHz 15 S 21 10 Gains, dB 5 0 -5 S -10 22 S 11 -15 -20 0 20 40 60 Frequency, GHz 80 TWA with internal ft-doubler cells UCSB PK Sundararajan 18 GHz S ADC UCSB S Jaganathan Design comparator is 75 GHz flip flop DC bias provided through 1 K resistors Integration obtained with 3 pF capacitors RTZ gated DAC Integrated Circuit 150 HBTs, 1.2 x 1.5 mm, 1.5 W Integrator-1 Integrator-2 Bias Rz Current Summing node Vin Bias RL RL C gm1 C gm2 C C RL RL Rz MasterSlave Flip-flop Clock Bias Bias Delayed Clock Idac Out 75 GHz HBT master-slave latch UCSB connected as Static frequency divider Thomas Mathew Hwe-Jong Kim technology: 400 Å base, 2000 Å collector HBT 0.7 um mask (0.6 um junction) x 12 um emitters 1.5 um mask (1.4 um junction) x 14 um collectors 1.8105 A/cm2 operation, 180 GHz ft, 260 GHz fmax simulations: 95 GHz clock rate in SPICE test data to date: tested, works over full 26-40 and 50-75 GHz bands 3.92 V, 224 mA, 0.88 W f =75GHz, f =37.5GHz f =69GHz, f =34.5GHz in out -0.03 0 -0.04 -0.02 -0.05 -0.04 Vout (Volts) Vout(Volts) in -0.06 -0.07 out ~3.5 dBm input power -0.06 -0.08 -0.08 -0.1 -0.09 -0.12 -0.1 modulation is synthesizer 6 GHz subharmonic -0.14 -0.11 0 50 100 Time(PS) 150 200 0 50 100 Time(ps) 150 200 MHBT slide State-of-art in HBTs, 2000: cutoff frequencies f SiGe ~0.1 um emitters f max f ~1 um emitters (0.4 um) InP f f 50 100 150 max AlGaAs/GaAs & GaInP/GaAs 0 (UCSB t.s. device) 200 f 250 ~1 um emitters max 300 350 Frequency, GHz InP HBTs today 2x faster, & more scalable: Johnson limit, 2x faster at 5x larger dimensions State-of-Art in HBTs, 2000: small-scale circuits amplifiers SiGe logic amplifiers InP logic 0 20 40 60 80 100 Frequency, GHz Si / SiGe has rough parity in logic with InP despite lower f, fmax due to higher current density, better emitter contacts Si/SiGe has significantly slower amplifiers What do we need for fast logic ? Gate Delay Determinedby : Depletioncapacitance charging throughthelogic swing VLOGIC Ccb Cbe ,depletion IC Depletioncapacitance charging throughthebase resistance Rbb Ccb Cbe ,depletion Supplyingbase collector storedcharge throughthebase resistance IC Rbb b c VLOGIC T helogic swing must be at least VLOGIC kT 6 Rex I c q ECL M-S latch out out in in clock clock clock clock Neither f nor fmax predicts digital speed CcbVlogic/Ic is very important collector capacitance reduction is critical increased III-V current density is critical Rex must be very low for low Vlogic at high Jc InP: Rbb , (b+c) , are already low, must remain so What HBT parameters determine logic speed ? Cje V/ I V/ I (kT/q) I Rex Rbb total Ccbx 33.5% 1.4% -1.3% 10.2% 43.8% b+c ) ( I/V) Ccbi 6.7% 0.1% 0.1% 6.8% 38% total 27.8% 0.4% 0.3% 2.8% 31.3% 12.3% 0.5% 0.9% 3.7% 17.5% 68.4% 12.3% 2.5% 0.1% 16.7% 100.0% SortingDelaysby capacitances : 44% chargingC je , 38% chargingCcb , only18% chargingCdiff (e.g. b c ) SortingDelaysby resistances and transit imes t : 68% from Vlogic / I c , 12% from( b c ), 17% from Rbb Rex has verystrongindirect effect,as Vlogic 6 kT / q I C Rex Caveats: assumes a specific UCSB InP HBT (0.7 um emitter, 1.2 um collector 3kÅ thick, 400 Å base, 1.5E5 A/cm^2) ignores interconnect capacitance and delay, which is very significant Why isn't base+collector transit time so important ? Under Small - Signal Operation: Q base dIC ( b c ) I C ( b c )I C ( b c ) Vbe Vbe dVbe kT / q Under Large- Signal Operation: Q base ( b c ) I dc ( b c ) I C VLOGIC VLOGIC Large- signal diffusion capacit ance reduced by ratioof VLOGIC kT / q , which is ~ 10 : 1 Depletioncapacit ances see no such reduction Very strong features of Si-bipolars Emitter Width: 0.1 um Emitter Current Density 10 mA/um2 Polysilicon Emitter Contact metal-semiconductor contact area >> emitter junction area low Rex Polysilicon base contact low sheet resistance in extrinsic base small extrinsic collector-base junction area InP HBT limits to yield: non-planar process Emitter contact Failure modes liftoff failure: emitter-base short-circuit emitter base contact base base sub collector S.I. substrate sub collector S.I. substrate Etch to base base excessive emitter undercut sub collector base contact S.I. substrate base Liftoff base metal base contact emitter contact sub collector base contact S.I. substrate base sub collector S.I. substrate planarization failure: interconnect breaks Emitter planarization, interconnects base base sub collector S.I. substrate sub collector S.I. substrate Yield degrades as emitters are scaled to submicron dimensions Submicron HBT scaling: Scaling HBTs for 2 x increased speed: 2 x thinner layers, 4 x narrower junctions 4 x higher current density, 4 x improved vertical contacts Results with submicron III-V HBT scaling: 300 GHz f, high (unmeasurable) fmax 6-dB 175 GHz amplifiers, 75 GHz true digital ICs Challenges with HBT scaling for fast digital : collector width scaling, current density, emitter resistivity high-yield submicron emitter & collector processes In Case of Questions Scaling Laws, Collector Current Density, Ccb charging time Base Push-Out (Kirk Effect) base emitter Vcb ( J / vsat qNd )(x2d / 2 ) sub collector collector Collector Depletion Layer Collapse Vcb (qNd J / vsat )(x2d / 2 ) base emitter sub collector J max J min 4vsat (Vcb ) / xd2 collector CcbVLOGIC / I C Acollector Tc VLOGIC 1 VLOGIC Acollector TC IC 2 VCB Aemitter 2vsat Collector capacitance charging time is reduced by thinning the collector while increasing current