Transcript CMOS Inverter Layout Click the LH mouse button to begin the animation Input Output Vdd well tap n-well substrate tap Vss.

CMOS Inverter Layout
Click the LH mouse button to begin the animation
Input
Output
Vdd
well tap
n-well
substrate
tap
Vss
CMOS Inverter Structure
Input
Output
Vdd
p+
well tap
n-well
metal
polysilicon
n-well
p+
p-substrate
polysilicon
n+
gate oxide
substrate
tap
n+
Vss
field oxide
CMOS Inverter Structure
Input
Output
Vdd
p+
well tap
n-well
metal
polysilicon
n-well
p+
p-substrate
polysilicon
n+
gate oxide
substrate
tap
n+
Vss
field oxide
Polysilicon Design Rule
Click the LH mouse button to begin the animation
Polysilicon Design Rule
Input
Output
No overlap of channel. Insufficient overlap of cut.
Polysilicon Design Rule
Input
Output
Faulty m1-p
connection
Current not
controlled
by gate
Current not
controlled
by gate
Polysilicon Design Rule
Input
Output
Adequate overlap of channel. Sufficient overlap of cut.
Polysilicon Design Rule
Input
Output