Transcript ECE 353 Introduction to Microprocessor Systems Week 10 Michael G. Morrow, P.E. Topics ADuC7026 External Memory Interface   Implementation Demultipexing Bus Timing  Bus cycle timing modification  Wait states and more Assessing.

ECE 353
Introduction to
Microprocessor Systems
Week 10
Michael G. Morrow, P.E.
Topics
ADuC7026 External Memory Interface
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Implementation
Demultipexing
Bus Timing
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Bus cycle timing modification
 Wait states and more
Assessing timing compatibility
Basic System Bus Operation
Address
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Unidirectional from CPU
Data
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Bidirectional
Control
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/RS or /RD – output from CPU
 Indicates a read operation in progress
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/WS or /WR – output from CPU
 Indicates a write operation in progress
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/WAIT or /READY – input to CPU
 Used by external device to signal that it is not able to
complete transfer yet (not present on ADuC7026)
ADuC7026 Bus Operation
The ADuC7026 external memory interface
consists of
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16-bit multiplexed address/data bus (AD15:0)
High address bit for 8-bit operation (A16)
 128kB regions require 17 bits of address
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Read and write strobes (/RS, /WS)
Memory select signals (/MS3:0)
 Internal decodes of upper 15 bits of address
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Byte enables (/BHE, /BLE)
 Used when memory interface is operating at 16-bit width
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Demultiplexing control signal (AE)
 Used to control logic that holds address valid to memory
system
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There is no WAIT/READY signal
Basic Read Cycle at Bus Level
Basic Write Cycle at Bus Level
ADuC7026 Demultiplexing
Multiplexed Signal Timing
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Read Cycle
Dealing with a multiplexed bus
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Demultiplexing by the device
Demultiplexing logic to create an address bus
Implementation
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Devices
Connections
AE timing
16-Bit Memory System
SRAM Timing Compatibility
In order to properly read and write the
device, we need to ensure that the
processor-to-memory interface is
compatible with the memory device.
This is accomplished by analyzing the
timing for all relevant parameters, and
ensuring that the operation can be
completed successfully.
We will work through the read cycle
analysis for the ADuC7026...
Assessing Timing Compatibility
Need to know whether CPU could operate
with the tAA for given device.
We designate a CPU characteristic tAVDV,
which is the delay from
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When the address becomes valid at the CPU
Until the data must be driven back to CPU
This establishes an upper bound on tAA
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tAA < tAVDV
Read cycle parameters
Read cycle timing control
Basic Read Cycle at Bus Level
Read Cycle Controls
System Timing Compatibility
Need to account for all delays in a
system to assess timing compatibility.
Consider this system.
Analyze the read timing with regard to:
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tAA – address access time
tACS – chip enable to valid data
tOE – output enable to valid data
tDF – output hold/float time
tAA – address access time
tACS – chip enable to valid data
tOE – output enable to valid data
tDF – output hold/float time
ADuC7026 External Memory
Interface Configuration
The external memory interface supports
four independently configured memory
regions, each of which is 128kB in size.
In order to use the external memory
interface, we need to
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Configure the required pins (GPxCON)
Enable the external interface (XMCFG[0] = 1)
Region enable and bus width (XMxCON)
Configure region for the desired bus timing
(XMxPAR)
ADuC7026 XMxCON
The XMxCON registers configure the bus width
and enable the interface for the respective
memory region. Only D[1:0] are used.
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XM0CON
XM1CON
XM2CON
XM3CON
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0x10000000-0x1001FFFF
0x20000000-0x2001FFFF
0x30000000-0x3001FFFF
0x40000000-0x4001FFFF
ADuC7026 XMxPAR
The XMxPAR MMR
configures the bus
timing for a region
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0x70FF at reset
[14:12] – AE extend
[9] – implements
bus turn-around
[8] – provides
additional hold time
[7:4],[3:0] – extend
write/read strobes
Write cycle timing control
Read cycle timing control
System Timing Compatibility
Consider again the system.
Analyzing write cycle timing.
SRAM write characteristics
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tWC
tAS, tAW, tCW
tWR
tWDS, tWDH
Write cycle controls
Timing Wrap-Up
Device characteristics are just part of the
total timing analysis picture
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Line/device capacitive loading and driver slew
rates
Transmission line effects and parasitic
reactance
Impedance mismatch and reflections
Skew and physical/electrical trace length
mismatch
Signal integrity
 Ensuring that signals are correct in spite of all of
the above issues and mutual coupling effects
Wrapping Up
Have a great Spring Break!
Complete Pre-Quiz #5 by the start of class
on Monday, April 9th
Homework #5 will be due on Wednesday,
April 11th
Reading for next week (interrupts and
exceptions)
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Textbook chapter 10
ADuC 74-75
ARM7 2.8-2.10
Basic Read Cycle
Basic Write Cycle
Read Cycle Parameters
Write Cycle Parameters
Read Cycle Controls
Write Cycle Controls
16-Bit Memory System
Ref
Ref