Transcript L23 – Arithmetic Logic Units Arithmetic Logic Units (ALU)  Modern ALU design ALU is heart of datapath  Ref: text Unit 15  9/2/2012 – ECE.

L23 – Arithmetic Logic Units
Arithmetic Logic Units (ALU)
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Modern ALU design
ALU is heart of datapath
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Ref: text Unit 15
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9/2/2012 – ECE 3561 Lect
9
Copyright 2012 - Joanne DeGroat, ECE, OSU
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Design of ALUs and Data Paths
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Objective: Design a General Purpose Data
Path such as the datapath found in a typical
computer.
A Data Path Contains:
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Registers – general purpose, special purpose
Execution Units capable of multiple functions
Have completed design of a dual ported
register set. Objective: Design ALU and
integrate with registers.
1/8/2012 - L3 Data Path
Design
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ALU Operations (integer ALU)
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Add
(A+B)
Add with Carry
(A+B+Cin)
Subtract
(A-B)
Subtract with Borrow (A-B-Cin)
[Subract reverse (B-A)]
[Subract reverse with Borrow (B-A-Cin)]
Negative A (-A)
Negative B (-B)
Increment A (A+1)
Increment B (B+1)
Decrement A (A-1)
Decrement B (B-1)
Logical AND
Logical OR
Logical XOR
1/8/2012 - L3 Data Path
Design
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Not A
Not B
A
B
Multiply Step or Multiply
Divide Step or Divide
Mask
Conditional AND/OR (uses
Mask)
Shift
Zero
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A High Level Design
From Hayes textbook on architecture.
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Design
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The AMD 2901 Bit Slice ALU
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Design
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The Architecture
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Design
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Arithmetic Logic Circuits
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The Brute Force Approach
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A more modern approach
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Design
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Arithmetic Logic Circuits
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A B
The Brute Force
Approach
Simple and
straightfoward
AB
AB
AB
A
Cout
FA
Cin
Function
N to 1 Mux
A more modern
approach
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Design
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Arithmetic Logic Circuits
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A B
The Brute Force
Approach
AB
AB
AB
A
Cout
FA
Cin
Function
N to 1 Mux
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A
A more modern
approach
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A
Logic
Unit
Where the logic unit
and the adder unit are
optimized
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Design
B
S
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B
Arithmetic
Unit
2 to 1 Mux
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A Generic Function Unit
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To Design – multifunction unit for logic operations
Desire a generic functional unit that can perform
4-to-1
many functions
G0
Mux
G1
G2
G3
G (A,B)
A
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B
A 4-to-1 mux will perform all basic logic
functions of 2 inputs – truth table input on data
inputs and function variable go to selects.
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Design
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Low level VLSI implementation
At the implementation
level the CMOS design
can be done with
transmission gates
Very important for VLSI
implementation
Implementation has a total
Of 16 transistors.
A
A’
B
B’
G0
G1
G(A,B
G2
G3
Could also use NAND
NOR implementation.
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Design
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Low level implementation
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An implementation in
pass gates (CMOS)
When the control
signal is a ‘1’ the value
will be transmitted
across the T gate
Otherwise it is an open
switch – i.e. high z
1/8/2012 - L3 Data Path
Design
A
A’
B’
B
G0
G1
G(A,B
G2
G3
A B A’ B’ G(A,B) AB A+B AxorB
0 0 1 1
G0
0
0
0
0 1 1 0
G1
0
1
1
1 0 0 1
G2
0
1
1
1 1 0 0
G3
1
1
0
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On FPGAs
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Can use the direct logic equation
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R <= (G0 AND NOT S1 AND NOT
(G1 AND NOT S1 AND
(G2 AND
S1 AND NOT
(G3 AND
S1 AND
S0) OR
S0) OR
S0) OR
S0);
And synthesize from this equation
Create a component for use in designs.
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The HDL code
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mux4to1 IS
PORT (G3,G2,G1,G0,S1,S0 : in std_logic;
R : OUT std_logic);
END mux4to1;
ARCHITECTURE one OF mux4to1 IS
BEGIN
R <= (G0 AND NOT S1 AND NOT S0) OR
(G1 AND NOT S1 AND
S0) OR
(G2 AND
S1 AND NOT S0) OR
(G3 AND
S1 AND
S0);
END one;
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And Quartis results
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Synthesis gives
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7 pins
1 LUT
RTL viewer results
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Logic functions summary
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0000
1000
1110
0110
1001
0111
0001
1100
0011
1010
0101
1111
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zero
AND
OR
XOR
XNOR
NAND
NOR
NOT A
A
NOT B
B
one
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Now - the arithmetic unit
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Typically integer add/subtract 2’s
complement
Can be simple – A ripple carry adder
Could also be a carry lookahead
Start with a simple ripple carry adder
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Do component based design
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Full adder
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Sum = a XOR b XOR c
Carry = ab + ac + bc
Create the HDL code and synthesize
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The HDL code – full adder
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY full_add IS
PORT (A,B,Cin : IN std_logic;
Sum,Cout : OUT std_logic);
END full_add;
ARCHITECTURE one OF full_add IS
BEGIN
Sum <= A XOR B XOR Cin;
Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);
END one;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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A multi-bit adder - structural
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY add8 IS
PORT (A,B : IN std_logic_vector (7 downto 0);
Cin : IN std_logic;
Cout : OUT std_logic;
Sum : OUT std_logic_vector (7 downto 0));
END add8;
ARCHITECTURE one OF add8 IS
COMPONENT full_add IS
PORT (A,B,Cin : IN std_logic;
Sum,Cout : OUT std_logic);
END COMPONENT;
FOR all : full_add USE ENTITY work.full_add(one);
SIGNAL ic : std_logic_vector (6 downto 0);
BEGIN
a0 : full_add PORT MAP (A(0),B(0),Cin,Sum(0),ic(0));
a1 : full_add PORT MAP (A(1),B(1),ic(0),Sum(1),ic(1));
a2 : full_add PORT MAP (A(2),B(2),ic(1),Sum(2),ic(2));
a3 : full_add PORT MAP (A(3),B(3),ic(2),Sum(3),ic(3));
a4 : full_add PORT MAP (A(4),B(4),ic(3),Sum(4),ic(4));
a5 : full_add PORT MAP (A(5),B(5),ic(4),Sum(5),ic(5));
a6 : full_add PORT MAP (A(6),B(6),ic(5),Sum(6),ic(6));
a7 : full_add PORT MAP (A(7),B(7),ic(6),Sum(7),Cout);
END one;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Synthesis results
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Synthesis gives
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26 pins – (a, b, sum, cin,
cout)
13 combinational LUTs
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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A second architecture
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY add8a2 IS
PORT (A,B : IN std_logic_vector (7 downto 0);
Cin : IN std_logic;
Cout : OUT std_logic;
Sum : OUT std_logic_vector (7 downto 0));
END add8a2;
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ARCHITECTURE one OF add8a2 IS
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SIGNAL ic : std_logic_vector (8 downto 0);
BEGIN
ic(0) <= Cin;
Sum <= A XOR B XOR ic(7 downto 0);
ic(8 downto 1) <= (A AND B) OR (A AND ic(7 downto 0)) OR (B AND ic(7 downto 0));
Cout <= ic(8);
END one;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The results now
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Resources -26 pins -12 LUTs
This is a carry lookahead implementation
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Lecture summary
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The adder was a simple ripple carry adder.
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Other Architectures
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Carry Lookahead
Carry select
Carry multiplexed
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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