Transcript FUTURE • Timing seemed good • However, only student to give feedback marked confusing (2 of 5 on clarity) and too fast (5 of.

FUTURE
• Timing seemed good
• However, only student to give feedback
marked confusing (2 of 5 on clarity) and too
fast (5 of 5 on pace).
• VLIW, MIMD not mean anything to EE
undergrads.
• In general, the taxonomy at the end is not the
big revelation it was for UCB CS grad
students
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Penn ESE680-002 Spring2007 -- DeHon
ESE680-002 (ESE534):
Computer Organization
Day 8: February 5, 2007
Computing Requirements and
Instruction Space
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Penn ESE680-002 Spring2007 -- DeHon
Previously
• Fixed and Programmable Computation
• Area-Time-Energy Tradeoffs
• VLSI Scaling
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Penn ESE680-002 Spring2007 -- DeHon
Today
• Computing Requirements
• Instructions
– Requirements
– Taxonomy
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Penn ESE680-002 Spring2007 -- DeHon
Computing Requirements
(review)
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Penn ESE680-002 Spring2007 -- DeHon
Requirements
• In order to build a general-purpose
(programmable) computing device, we
absolutely must have?
–_
–_
–_
–_
–_
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Penn ESE680-002 Spring2007 -- DeHon
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Penn ESE680-002 Spring2007 -- DeHon
Primitive compute
elements enough?
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Penn ESE680-002 Spring2007 -- DeHon
Compute and Interconnect
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Penn ESE680-002 Spring2007 -- DeHon
Sharing
Interconnect
Resources
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Penn ESE680-002 Spring2007 -- DeHon
Sharing Interconnect and Compute Resources
What role are the
memories playing
here?
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Penn ESE680-002 Spring2007 -- DeHon
Memory block or
Register File
Interconnect:
moves data from
input to storage
cell;
or from storage
cell to output.
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Penn ESE680-002 Spring2007 -- DeHon
What do I need to be able to use this circuit properly?
(reuse it on different data?)
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Penn ESE680-002 Spring2007 -- DeHon
Requirements
• In order to build a general-purpose
(programmable) computing device, we
absolutely must have?
– Compute elements
– Interconnect: space
– Interconnect: time (retiming)
– Interconnect: external (IO)
– Instructions
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Taxonomy
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Penn ESE680-002 Spring2007 -- DeHon
• Distinguishing feature of programmable
architectures?
– Instructions -- bits which tell the device
how to behave
Compute
0000 00
net0
Penn ESE680-002 Spring2007 -- DeHon
010
add
11 0110
mem slot#6
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Focus on Instructions
• Instruction organization has a large
effect on:
– size or compactness of an architecture
– realm of efficient utilization for an
architecture
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Penn ESE680-002 Spring2007 -- DeHon
Terminology
• Primitive Instruction (pinst)
– Collection of bits which tell a single bitprocessing element what to do
– Includes:
• select compute operation
• input sources in space
– (interconnect)
• input sources in time
– (retiming)
Compute
0000 00
net0
010
add
11 0110
mem slot#6
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Penn ESE680-002 Spring2007 -- DeHon
Computational Array Model
• Collection of
computing elements
– compute operator
– local storage/retiming
• Interconnect
• Instruction
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Penn ESE680-002 Spring2007 -- DeHon
“Ideal” Instruction Control
• Issue a new instruction to every
computational bit operator on every
cycle
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Penn ESE680-002 Spring2007 -- DeHon
“Ideal” Instruction Distribution
• Why don’t we do this?
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Penn ESE680-002 Spring2007 -- DeHon
“Ideal” Instruction Distribution
• Problem: Instruction bandwidth (and
storage area) quickly dominates
everything else
– Compute Block ~ 1Ml2 (1Kl x 1Kl)
– Instruction ~ 64 bits
– Wire Pitch ~ 8l
– Memory bit ~ 1.2Kl2
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Penn ESE680-002 Spring2007 -- DeHon
64x8l=512l
Two instructions in 1024l
Instruction Distribution
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Distribution
Distribute from both sides = 2x
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Distribution
Distribute X and Y = 2x
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Distribution
• Room to distribute 2 instructions across
PE per metal layer (1024 = 2864)
• Feed top and bottom (left and right) = 2
• Two complete metal layers = 2
•  8 instructions / PE Side
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Distribution
• Maximum of 8 instructions per PE side
• Saturate wire channels at 8N = N
•  at 64 PE
– beyond this:
• instruction distribution dominates area
• Instruction consumption goes with area
• Instruction bandwidth goes with
perimeter
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Distribution
• Beyond 64 PE, instruction bandwidth
dictates PE size
PEarea 4N
=N
(648l)
PEarea =16Kl2N
• As we build larger arrays
processing elements become less dense
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Penn ESE680-002 Spring2007 -- DeHon
Avoid Instruction BW Saturation?
• How might we avoid this?
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Memory
Requirements
• Idea: put instruction memory in array
• Problem: Instruction memory can
quickly dominate area, too
– Memory Area = 641.2Kl2/instruction
– PEarea = 1Ml2 + (Instructions)  80Kl2
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Pragmatics
• Instruction requirements could dominate
array size.
• Standard architecture trick:
– Look for structure to exploit in “typical
computations”
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Penn ESE680-002 Spring2007 -- DeHon
Typical Structure?
• What structure do we usually expect?
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Penn ESE680-002 Spring2007 -- DeHon
Two Extremes
• SIMD Array
(microprocessors)
– Instruction/cycle
– share instruction across array
of PEs
– uniform operation in space
– operation variance in time
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Penn ESE680-002 Spring2007 -- DeHon
Two Extremes
• SIMD Array
(microprocessors)
– Instruction/cycle
– share instruction
across array of PEs
– uniform operation in
space
– operation variance in
time
• FPGA
– Instruction/PE
– assume temporal
locality of instructions
(same)
– operation variance in
space
– uniform operations in
time
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Penn ESE680-002 Spring2007 -- DeHon
Placing Architectures
• What programmable architectures
(organizations) are you familiar with?
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Penn ESE680-002 Spring2007 -- DeHon
• What differentiates a VLIW from a
multicore?
– E.g.
• 4-issue VLIW vs.
• 4 single-issue processors
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Penn ESE680-002 Spring2007 -- DeHon
Gross Parameters
• Instruction sharing width
– SIMD width
– granularity
• Instruction depth
– Instructions stored locally per compute
element
• pinsts per control thread
– E.g. VLIW width
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Penn ESE680-002 Spring2007 -- DeHon
Architecture Instruction
Taxonomy
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Penn ESE680-002 Spring2007 -- DeHon
Instruction Message
• Architectures fall out of:
– general model too expensive
– structure exists in common problems
– exploit structure to reduce resource
requirements
• Architectures can be viewed in a unified
design space
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Penn ESE680-002 Spring2007 -- DeHon
Admin
• Instruction assignment due Wednesday
• Reading for today and Wed. on web
• Try GRW262 for André Office Hours this
week
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Penn ESE680-002 Spring2007 -- DeHon
Big Ideas
[MSB Ideas]
• Basic elements of a programmable
computation
– Compute
– Interconnect
• (space and time, outside system [IO])
– Instructions
• Instruction resources can be significant
– dominant/limiting resource
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Penn ESE680-002 Spring2007 -- DeHon
Big Ideas
[MSB-1 Ideas]
• Two key functions of memory
– retiming
– instructions
• description of computation
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Penn ESE680-002 Spring2007 -- DeHon