Transcript AE0B36APO Computer Architectures Computer Architectures

Computer Architectures
Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated
Czech Technical University in Prague, Faculty of Electrical Engineering
AE0B36APO Computer Architectures
Ver.1.10
1
Original Desktop/Workstation 680X0
Feature
Data bus
Addr bus
Misaligned Addr
Virtual memory
Instruct Cache
Data Cache
Memory manager
ATC entries
FPU interface
built-in FPU
Burst Memory
Bus Cycle type
Data Bus Sizing
Power (watts)
at frequency of
MIPS/kDhryst.
Transistors
Introduction
68000
16
23
-
'EC000
68010
8/16
16
23
23
Yes
3
68451 or 68851
asynchronous
1.2
0.13-0.26
0.13
8.0
8-16
8
1.2/2.1
2.5/4.3
68k
84k
1979
1982
AE0B36APO Computer Architectures
68020
68030
8/16/32
8/16/32
32
32
Yes
Yes
Yes
Yes
256
256
256
68851
Yes
22
68881 or 68882
Yes
both
Yes
Yes
1.75
2.6
16-25
16-50
6.5/11
14/23
190k
273k
1984
1987
68040
68060
32
32
32
32
Yes
Yes
Yes
Yes
4096
8192
4096
8192
Yes
Yes
64/64
64/64
Internal FPU
Yes
Yes
Yes
Yes
synchronous
use 68150
4-6
3.9-4.9
25-40
50-66
35/60
100/300
1,170k
2,500k
1991
1994
2
M68xxx/CPU32/ColdFire – Basic Registers Set
User programming
model registers
31
16 15
8 7
0
D0
D1
D2
D3
D4
D5
D6
D7
16 15
DATA REGISTERS
0
A0
A1
A2
A3
A4
A5
A6
16 15
ADDRESS REGISTERS
0
A7 (USP)
USER STACK POINTER
0
15
8 7
0
31
Supervisor/system
programing model
basic registers
PC
PROGRAM COUNTER
CCR
CONDITION CODE REGISTER
0
16 15
0
A7# (SSP)
15
8 7
0
(CCR)
31
SR
3 2
VECTOR BASE REGISTER
0
SFC
DFC
AE0B36APO Computer Architectures
STATUS REGISTER
0
VBR
31
SUPERVISOR STACK
POINTER
ALTERNATE FUNCTION
CODE REGISTERS
3
Status Register – Conditional Code Part
USER BYTE
(CONDITION CODE REGISTER)
SYSTEM BYTE
15
T1
14
T0
13
S
12
0
TRACE
ENABLE
11
0
10
I2
9
I1
8
I0
INTERRUPT
PRIORITY MASK
7
0
6
0
5
0
4
X
3
N
2
Z
1
V
0
C
EXTEND
NEGATIVE
SUPERVISOR/USER
STATE
ZERO
OVERFLOW
CARRY
●
●
●
●
N – negative ... = 1 when the most significant bit of the
result is set; otherwise cleared. (the result is negative for
two's complement representation)
Z – zero ... = 1 when result is zero – all bits are zero
V – overflow .. = 1 when an arithmetic overflow occurs
implying that the result cannot be represented in the
operand size (signed case for add, sub, …)
C – carry ... = 1 when when a carry out of the most
significant bit occurs (add) or a borrow occurs (sub)
AE0B36APO Computer Architectures
4
Status Register – System Byte
USER BYTE
(CONDITION CODE REGISTER)
SYSTEM BYTE
15
T1
14
T0
13
S
12
0
TRACE
ENABLE
11
0
10
I2
9
I1
8
I0
INTERRUPT
PRIORITY MASK
7
0
6
0
5
0
4
X
3
N
2
Z
1
V
0
C
EXTEND
NEGATIVE
SUPERVISOR/USER
STATE
ZERO
OVERFLOW
CARRY
●
T1, T0 – trace … if some of these bits is set then
exception is generated after every instruction execution
or when program flow changes (jump, call, return)
S – supervisor … if set to 1 then CPU runs in the
supervisor state/mode and SP maps to SSP. Else CPU
runs in user mode, SP maps to USP and changes to the
system byte are not possible and user mode privileges
rules/restrictions are applied to memory access
(controlled by MMU).
AE0B36APO Computer Architectures
●
●
I2, I1, I0 - interrupt mask … up to this interrupt priority
5
Addressing Modes of 68000
●
Up to 14 addressing modes for operand selection exists
for some architecture family members. The next
described symbols convention is used for the full
instructions description/specification.
AE0B36APO Computer Architectures
6
Addressing – register naming convention
EA - effective address
● An
- address register n, example: A3
● Dn
- data register n, example: D3
● Rn
- any address or data register
● Xn.SIZE*SCALE index addressing with scaling
– Xn any address or data register in the role of index/offset
– SIZE index size W (16-bit) or L (32-bit)
– SCALE - multiplier of the index 1, 2, 4 or 8
● PC
- program counter
● SR
- status register
● SP
- stack pointer (A7 - USP or SSP)
● CCR - conditional code register, lower byte of SR
● USP - user stack pointer
● SSP - supervisor stack pointer režimu
●
AE0B36APO Computer Architectures
7
Addressing – direct operands and indirection symbolic
●
●
●
●
●
●
dn offset, n bits long
bd base address up to 32 bits
L
operand length 32 bits (long-word)
W
operand length 16 bits (word)
B
operand length 8 bits (byte)
(An) brackets are used to denote that memory
cell pointed by value between brackets is
source/destination
AE0B36APO Computer Architectures
8
Addressing modes – basic 68000 modes
●
●
●
●
●
●
●
●
Rn operand represents value of data Dn or address An
register
(An) memory content at the address specified by An
(An)+ memory content at An with following An increment by
value equivalent to the operand length (post-increment)
-(An) the An register is decremented by operand size first and
then specifies memory located operand (pre-decrement)
(d16,An) memory at An + 16-bit sign extended offset
(d8,An,Xn) memory at An + 8-bit sign extended offset + index
register (another Am or Dm) which can be eventually limited to
lower 16 bits, index can be multiplied by 1, 2, 4 or 8 for
CPU32 and 68020+ processors
(xxx).W 16-bit absolute address – upper and lower 32kB
(xxx).L 32-bit absolute address
AE0B36APO Computer Architectures
9
Addressing – extended index modes and PC relative modes
●
●
●
●
(bd,An,Xn*SCALE) memory address is the sum of address
register, index register multiplied by SCALE (1, 2, 4 or 8) and
up-to 32-bit base displacement (0, 16 or 32 bits), the mode
encoding allows to suppress/skip index value, even address
register can be suppressed, this mode is implemented on
CPU32 and 68020+
(d16,PC) addressing relative to PC with 16-bit sign extended
offset
(d8,PC,Xn) addressing relative to PC with 8-bit sign extended
offset and index register (scaled) added
(bd,PC,Xn*SCALE) addressing relative to PC with offset size
up to 32 bits, index multiplied by scale; additional options are
the same as for the case where address register is used as an
address base
AE0B36APO Computer Architectures
10
Addressing – extension found on 68020-40
The next addressing modes are listed for completeness. They are
not implemented on CPU32 or ColdFire family. Only 68020 up to
68040 knows them. Even 68060 emulates them in a software.
●
●
●
●
([bd,An],Xn,od) the memory operand address is computed as
sum of value stored at address An+bd, outer displacement od
and index
([bd,PC],Xn,od) the same but PC relative
([bd,An,Xn],od) the operand address is given by value at
address An+Xn+bd which is then increased by up-to 32-bit
outer displacement od
([bd,PC,Xn],od) the same but PC relative
AE0B36APO Computer Architectures
11
Instruction Format and Address Mode Encoding
SINGLE EA INSTRUCTION FORMAT
15
14
13
12
11
10
9
8
7
6
X
X
X
X
X
X
X
X
X
X
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BRIEF FORMAT EXTENSION WORD
15
14
D/A
12
REGISTER
11
W/ L
10
9
SCALE
8
7
0
0
DISPLACEMENT
FULL FORMAT EXTENSION WORD(S)
15
D/A
14
12
REGISTER
11
W/ L
10
9
SCALE
8
7
6
5
4
3
1
BS
IS
BD SIZE
0
2
0
I/IS
BASE DISPLACEMENT (0, 1, OR 2 WORDS)
Field
Instruction
Register
Extension
Register
D/A
Definition
Definition
Base Register Suppress
General Register Number
0 = Base Register Added
1 = Base Register Suppressed
Index Register Number
IS
Index Suppress
Index Register Type
0 = Evaluate and Add Index Operand
0 = Dn
1 = Suppress Index Operand
1 = An
BD SIZE
Base Displacement Size
W/L
Word/Long Word Index Size
00 = Reserved
0 = Sign-Extended Word
01 = Null Displacement
1 = Long Word
10 = Word Displacement
Scale
Scale Factor
11 = Long-Word Displacement
00 = 1
I/IS *
Index/Indirect Selection
01 = 2
Indirect and Indexing Operand
10 = 4
Determined in Conjunction with Bit 6,
11 = 8
Index Suppress
*Memory indirect addressing will cause illegal instruction trap; must be = 000 if IS = 1
AE0B36APO Computer Architectures
Field
BS
12
680x0 Fixed Point Instruction Set
M n e m o n ic
ABCD
ADD
AND
ASL
ASR
B< c c >
BCHG
BCLR
BRA
BSE T
BSR
BTST
CHK
CLR
CM P
DB< c c >
D IVS
D IVU
E OR
E XG
E XT
JM P
JSR
LE A
LIN K
LSL
LSR
D e s c rit p t io n
Ad d De c im a l w it h E xt e n d
Ad d
Log ica l AND
Ar it h m e t ic Sh ift Le ft
Ar it h m e t ic Sh ift Rig h t
Br a n ch Co n d it ion a lly
Bit Te s t a n d Ch a n g e
Bit Te s t a n d Cle a r
Br a n ch Alw a ys
Bit Te s t a n d Se t
Br a n ch t o Su b r ou t in e
Bit Te s t
Ch e c k Re ig s t e r Ag a in s t Bo u n d s
Cle a r Op e r a n d
Co m p a r e
De c r e m e n t a n d Br a n ch Co n d it ion a lly
Sig n e d Divid e
Un s ig n e d Divid e
E xc lu s ive OR
E xch a n g e Re g is t e r s
Sig n E xt e n d
Ju m p
Ju m p t o Su b r ou t in e
Loa d E ffe ct ive Ad d r e s s
Lin k St a c k
Log ica l Sh ift Le ft
Log ica l Sh ift Rig h t
AE0B36APO Computer Architectures
M n e m o n ic
M OVE
M ULS
M ULU
N BCD
NE G
N OP
N OT
OR
PEA
RE SE T
ROL
ROR
RO XL
RO XR
RTD
RTE
RTR
RTS
SBCD
S< c c >
STOP
SU B
SWAP
TAS
TRAP
TRAP V
TST
U N LK
D e s c rit p t io n
M o ve So u r c e t o De s t in a t ion
Sig n e d M u lt ip ly
Un s ig n e d M u lt ip ly
Ne g a t e De c im a l w it h E xt e n e d
Ne g a t e
N o Op e r a t ion
On e 's Co m p le m e n t
Lo g ic a l OR
P u s h e ffe c t ive Ad d r e s s
Re s e t E xt e r n a l De vic e s
Ro t a t e Le ft w it h ou t E xt e n d
Ro t a t e Rig h t w it h ou t E xt e n d
Ro t a t e Le ft w it h E xt e n d
Ro t a t e Rig h t w ih t E xt e n d
Re t u r n a n d De lo c a t e
Re t u r n fr o m E xc e p t ion
Re t u r n a n d Re s t or e
Re t u r n fr o m Su b r ou t in e
Su b t r a ct De c im a l w ih t E xt e n d
Se t Co n d it ion a l
St o p
Su b t r a ct
Sw a p d a t a r e g is t e r h a lve s
Te s t a n d Se t Op e r a n d
Tr a p
Tr a p o n Ove r flo w
Te s t
Un lin k St a c k F r a m e
13
Extended Instructions of CPU32 and 68020
Mn em o n ic
Des c rip tio n
CPU32
yes
M68020
yes
Bcc
Supports 32-Bit Displacement
BFxxxx
Bit Field Instructions (BFCHG, BFCLR, BFEXTS,
BFEXTU, BFFO, BFINS, BFSET, BFTST)
BGND
Background Operation
yes
BKPT
New Instruction Function
yes
yes
BRA
Supports 32-Bit Displacement
yes
yes
BSR
Supports 32-Bit Displacement
yes
yes
CALLM
New Instruction
CAS,CAS2
New Instruction
CHK
Supports 32-Bit Operands
yes
yes
CHK2
New Instruction
yes
yes
CMP1
Supports Program Counter Relative Addressing
yes
yes
CMP2
New Instruction
yes
yes
cp
Coprocessor Instructions
DIVS/DIVU
Supports 32-Bit and 64-Bit Operations
yes
yes
EXTB
Supports 8-Bit Extend to 32 Bits
yes
yes
LINK
Supports 32-Bit Displacement
yes
yes
LPSTOP
New Instruction
yes
MOVEC
Supports New Control Registers
yes
yes
MULS/MULU
Supports 32-Bit Operands and 64-Bit Results
yes
yes
PACK
New Instruction
RTM
New Instruction
yes
yes
yes
yes
yes
yes
TBLSN,TBLU N
TBLS,TBLU
New Instruction
yes
TST
Supports Program Counter Relative, Immediate, and
An Addressing
yes
yes
TRAPcc
New Instruction
yes
yes
UNPK
New Instruction
AE0B36APO Computer Architectures
yes
14
Procedure Calling and LINK/UNLK Instructions
f(1,2,3);
int f(int a, int b, int c )
{ return a + b + c; }
movel #3,%sp@f: linkw %fp,#0
pea 3
movel %a6,%sp@movel #2,%sp@movel %a7,%a6
movel #1,%sp@movel %d2,%sp@jsr f
subql #20,%sp
ret_pc:
addql #12,%sp
movel %fp@(8),%d0
lea %sp@(12),%sp
addl %fp@(12),%d0
addl %fp@(16),%d0
m68k calling convention
addql #20,%sp
movel %sp@+,%d2
unlk %fp
movel %a6,%a7
movel %sp@+,%a6
rts
fixed A7 = SP, (A6 = FP)
return D0, D0+D1
parameters on stack
clobberable registers D0, D1, A0, A1
AE0B36APO Computer Architectures
0xffffffff
sp'
fp+16
3 (c)
fp+12
2 (b)
fp+8
1 (a)
fp+4
ret_pc
fp
save fp
fp-4
save d2
fp-8
local
var
sp
arg
to next
call
params/
args to f
pc/regs
save
area
function f
local
variables
0x00000000
15
Instruction Timing for CPU32
Instructions
MOVE.W A1, (A0)+
ADDQ.W #1, (A0)
CLR.W
1
2
3
4
5
6
7
$30 (A1)
8
9
0
1
2
3
4
5
6
7
8
CLOCK
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
EXECUTION
TIME
WRITE
FOR 1
MOVE A1,(A0)+
1 PREFETCH
EA FETCH
ADDQ
MOVE.W A1,(AO)+
AE0B36APO Computer Architectures
READ
FOR 2
WRITE
FOR 2
ADDQ
TO <EA>
ADDQ.W #1,(A0)
2 PREFETCH
3 PREFETCH
EA CALC
CLR
3 PREFETCH
WRITE
FOR 3
CLR
<EA>
CLR.W $30(A1)
16
Module pads/pins/signals
68000, 68008, 68EC000
ADDRESS
Vcc
GND
BUS
CLK
DATA
BUS
A23-A0
D15-D0
AS
R/W
PROCESSOR
ASYNCHRONOUS
FC0
UDS
BUS
FC1
LDS
CONTROL
FC2
DTACK
STATUS
E
MC6800
PERIPHERAL
CONTROL
VMA
VPA
BR
BG
BGACK
BERR
IPL0
RESET
IPL1
HALT
IPL2
MODE
AVEC
BUS
ARBITRATION
CONTROL
INTERRUPT
SYSTEM
CONTROL
AE0B36APO Computer Architectures
CONTROL
17
68030 Signals
IPL0
FUNCTION CODES
FC2-FC0
ADDRESS BUS
A31-A0
IPL1
IPL2
IPEND
DATA BUS
INTERRUPT
CONTROL
AVEC
D31-D0
BR
SIZ0
TRANSFER
SIZE
BG
SIZ1
BGACK
OCS
ECS
R/W
BUS ARBITRATION
CONTROL
RESET
MC68EC030
HALT
BERR
BUS EXCEPTION
CONTROL
RMC
AS
ASYNCHRONOUS
BUS CONTROL
STERM
DS
DBEN
SYNCHRONOUS
BUS CONTROL
REFILL
DSACK0
STATUS
DSACK1
CDIS
EMULATOR
SUPPORT
CIIN
CACHE
CONTROL
AE0B36APO Computer Architectures
CIOUT
CLK
CBREQ
VCC (10)
CBACK
GND (14)
18
68030 Block Diagram
MICROSEQUENCER AND
CONTROL
CONTROL
STORE
INSTRUCTION PIPE
STAGE
D
STAGE
STAGE
C
B
CACHE
HOLDING
REGISTER
(CAHR)
INTERNAL
DATA
BUS
CONTROL
LOGIC
INSTRUCTION
CACHE
INSTRUCTION
ADDRESS
BUS
ADDRESS
BUS
ADDRESS
PADS
ADDRESS
EXECUTION UNIT
PROGRAM
COUNTER
SECTION
MMU
+22 ATC
ADDRESS
SECTION
DATA
SECTION
SIZE
MULTIPLEXER
DATA
PADS
DATA
BUS
68030 Only
ACCESS
CONTROL
UNIT
68030 Only
ADDRESS
BUS
MISALIGNMENT
MULTIPLEXER
BUS CONTROLLER
WRITE PENDING PREFETCH PENDING
BUFFER
BUFFER
MICROBUS
CONTROLLER
DATA
ADDRESS
BUS
DATA
CACHE
68030 Only
BUS CONTROL
SIGNALS
AE0B36APO Computer Architectures
19
Dynamic Bus Sizing for CPU32(+) and 68020/030
S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4
CLK
A31-A2
A1
A0
FC2-FC0
SIZ1
4 bytes
3 bytes
2 bytes
1 byte
SIZ0
R/W
AS
DS
DSACK1
DSACK0
DBEN
AE0B36APO Computer Architectures
D31-D24
OP0
OP1
OP2
OP3
D23-D16
OP1
OP1
OP3
OP3
D15-D8
OP2
OP2
OP2
OP3
D7-D0
OP3
OP3
OP3
OP3
20
68060 – User Mode
31
0
79
0
D0
D1
FP0
FP1
D2
DATA
REGISTERS
FP2
FLOATING-POINT
DATA
REGISTERS
D3
D4
D5
FP3
FP4
FP5
D6
D7
FP6
FP7
A0
31
A1
A2
ADDRESS
REGISTERS
FP CONTROL REGISTER
15
0
0
FPCR
A3
FP STATUS REGISTER
FPSR
A4
A5
FP INSTRUCTION ADDRESS REGISTER
FPIAR
A6
A7/USP
PC
PROGRAM COUNTER
CCR
CONDITION CODE REGISTER
AE0B36APO Computer Architectures
USER STACK POINTER
21
68060 – System Mode
31
0
(CCR)
PCR
PROCESSOR CONFIGURATION REGISTER
A7/SSP
SUPERVISOR STACK POINTER
SR
STATUS REGISTER (CCR ALSO IN THE USER PROGRAMMING MODEL)
VBR
VECTOR BASE REGISTER
SFC
SOURCE FUNCTION CODE
DFC
DESTINATION FUNCTION CODE
CACR
CACHE CONTROL REGISTER
URP
AE0B36APO Computer Architectures
USER ROOT POINTER REGISTER
SRP
SUPERVISOR ROOT POINTER REGISTER
TC
TRANSLATION CONTROL REGISTER
DTT0
DATA TRANSPARENT TRANSLATION REGISTER 0
DTT1
DATA TRANSPARENT TRANSLATION REGISTER 1
ITT0
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0
ITT1
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1
BUSCR
BUS CONTROL REGISTER
22
68060 – Exception vectors Assignments
Vector
Number(s)
Vector
Offset (Hex)
Stack Frame
Format
0
1
2
3
4
5
6
7
8
9
10
11
11
11
12
13
14
15
16-23
24
25
26
27
28
29
30
31
32-47
000
004
008
00C
010
014
018
01C
020
024
028
02C
02C
02C
030
034
038
03C
040-05C
060
064
068
06C
070
074
078
07C
080-0BC
4
2
0
2
2
2
0
2
0
0
2
4
48-55
0C0-0DC
-
0
0
0
0
0
0
0
0
0
0
0
0
Stacked
Program
Counter *
fault
fault
next
next
next
fault
next
fault
fault
next
next
next
fault
next
next
next
next
next
next
next
next
next
next
-
Assignment
Reset Initial SSP
Reset Initial PC
Access Fault
Address Error
Illegal Instruction
Integer Divide-by-Zero
CHK, CHK2 Instructions
TRAPcc, TRAPV Instructions
Privilege Violation
Trace
Line 1010 Emulator (Unimplemented A-Line Opcode)
Line 1111 Emulator (Unimplemented F-Line Opcode)
Floating-Point Unimplemented Instruction
Floating-Point Disabled
Emulator Interrupt
Only 68020, 68030 - Coprocessor Protocol Violation
Format Error
Uninitialized Interrupt
(Unassigned, Reserved)
Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
TRAP #0-15 Instruction Vectors
Floating-Point Exceptions#
56
0E0
Only 68030, 68851 - PMMU Configuration
57
0E4
Only 68851 - PMMU Illegal Operation
58
0E8
Only 68851 - PMMU Access Level Violation
59
0EC
(Unassigned, Reserved)
60
0F0
0
fault
Unimplemented Effective Address
61
0F4
0
fault
Unimplemented Integer Instruction
62-63
0F8-0FC
(Unassigned, Reserved)
64-255
100-3FC
0
next
User Defined Vectors (192)
*For the Access Fault exception PC and internal CPU state necessary to finish instruction is stored "fault" refers to the PC of the instruction that caused
the exception. "next" refers to the PC of the next instruction that follows the instruction that caused the fault.
AE0B36APO Computer Architectures
23
68060 – Paging
Virtual address format and bit mapping to page table levels
31
25 24
7 BITS
ROOT INDEX
FIELD
(RI)
18 17
7 BITS
POINTER INDEX
FIELD
(PI)
13 12 11
8K PAGE
4K PAGE
PAGE INDEX
FIELD
(PGI)
0
13 BITS - 8K PAGE
12 BITS - 4K PAGE
PAGE OFFSET
Page table descriptors
31
9
POINTER TABLE ADDRESS
ROOT TABLE DESCRIPTOR (ROOT LEVEL)
9
31
PAGE TABLE ADDRESS
POINTER TABLE DESCRIPTOR (POINTER LEVEL)
31
12 11 10 9
PHYSICAL ADDRESS
UR G U1
4K PAGE DESCRIPTOR (PAGE LEVEL)
31
13 12 11 10 9
PHYSICAL ADDRESS
UR UR G U1
8K PAGE DESCRIPTOR (PAGE LEVEL)
31
DESCRIPTOR ADDRESS
INDIRECT PAGE DESCRIPTOR (PAGE LEVEL)
AE0B36APO Computer Architectures
8
X
7 6 5
X X X
4 3 2 1 0
X U W UDT
8
X
7 6 5
X X X
4
X
3 2 1 0
U W UDT
8 7 6 5
U0 S
CM
4 3 2 1 0
M U W PDT
8 7 6 5
U0 S
CM
4 3 2 1 0
M U W PDT
7
6
5
4
3
2
1 0
PDT
24
68060 – Page Table and Address Translation
31
FIELDS OF
LOGICAL ADDRESS
25 24
7 BITS
7 BITS
ROOT INDEX FIELD
TASK-A
LOGICAL ADDRESS
18 17
POINTER INDEX FIELD PAGE INDEX FIELD
(RI)
(PI)
$76543210 = 0 1 1 1 0 1 1
$3B
TABLE ENTRY # =
ADDRESS OFFSET = $EC
13 12 11
8K PAGE
4K PAGE
(PGI)
0 0 1 0 1 0 1
$15
$54
TABLE $00
0 0 0 0 1
PAGE OFFSET
1 0 0 1 0 0 0 0 1 0 0 0 0
$01
$04
$1210
TABLE $00
TABLE $00
RESIDENT UDT
INVALID PDT
INVALID UDT
TASK A
0
13 BITS - 8K PAGE
12 BITS - 4K PAGE
RESIDENT PDT
ROOT POINTER
URP or SRP
$3B
W-BIT SET
INDIRECT PDT
TABLE $3B
TABLE $15
ROOT POINTER
TASK B
URP or SRP
W-BIT CLEAR
ROOT-LEVEL
TABLES
AE0B36APO Computer Architectures
$15
$00003000
POINTER-LEVEL
TABLES
$01 FRAME ADDR*
PAGE-LEVEL
TABLES
PHYSICAL
ADDRESS
25
68060 – Instruction/Data Cache Memory Organization
PHYSICAL ADDRESS
31
4 3 0
11 10
TAG DATA/TAG REFERENCE
INDEX
LINE 3
LINE 2
LINE 1
LINE 0
PHYSICAL
SET SELECT
PA10-PA4
PA31-PA11
SET 0
TAG
STATUS LW0 LW1LW2LW3
SET 128 TAG
STATUS LW0LW1LW2LW3
SET 1
DATA OR
INSTRUCTION
TRANSLATED
PHYSICAL
ADDRESS
PA31-PA11
MUX
3
2
1
COMPARATOR
AE0B36APO Computer Architectures
0
LINE SELECT
HIT 3
HIT 2
HIT 1
LOGICAL
OR
HIT
HIT 0
26
The Evolution of Motorola/FreeScale's CPUs and MCUs
CPU32/683xx
10 Versions
MPC5xx
Hardware Compatability
MCORE
2000
68HC16
18Versions
68000
68HC12
New 16-bit MCU Standard
68HC11
6800
50 Versions
68HC05
160 Versions
AE0B36APO Computer Architectures
32-Bit
68020
PowerPC
16-Bit
RISC Core
68HC08
New 8-bit MCU Standard
Software Compatability
8-Bit
68040/60
MPC601
27
32-bit MCUs and CPUs for embedded applications
MPC555/565
Industrial Control/
Motion Control
CPU32
core
MC68332
MC68396
MC68376 +Flash
MC68336 +CAN
+TPU
+QSPI
+SCI
+ADC
NetComm
68000
core
M68302 Fam
+2-3 SCCs
+SCP
+DMA
PowerPC
MCore
CPU32
core
MC68360 Fam
+7 ser. I/Fs
+DRAM-C
+DMAs
+FPU, 2xTPU3
+MIOS1, 2xQADC
+2xTouCAN
MPC505/9 +QSPI, 2xSCI
+FPU
+6/6/26k RAM
+4/28k SRAM +448k Flash
PowerPC
core
MPC860-Fam
1.6-75
MIPs
MPC821-Fam
32-75
MIPs
+8 ser I/F
+UPM
+MAC
+6 ser I/F
+LCD-C
FlexCore for
Consumer and
Industrial Control
68000
core
MC68306A
+DUART
+DRAM-C
+IIC
MCF5407
MC68328
+LCD-C
+UART
+RTC
AE0B36APO Computer Architectures
ColdFire MCF5206
+DUART
+DRAM-C
core
+IIC
3.5-42
MIPs
MCF5307
+G3-core
+DMA
+G4-core
+16k/8k
I/D cache
+MAC, div
+DRAM-C
2xGTP, IIC
2xUART
1.6-75
MIPs
28
683xx/CPU32(+) Microcontroller Family
Feature
Core CPU
Data Bus
Addr Bus
Misaligned Addr
Development Int.
TPU (timer)
UART
DRAM controller
Static Ram
Flash EEPROM
A/D Converter
Serial Ports
SPI interface
DMA
Timer
Parallel Ports (bits)
Chip Selects X
More ...
Clock speed Mhz
Power voltage
Power (watts)
at frequency of
AE0B36APO Computer Architectures
68332
CPU32
8/16
24
BDM
Yes
68376
CPU32
8/16
24
BDM
Yes
2K
3.5K+4K
1xSCM
1xQSM
8/10 bits
1xSCM
1xQSM
up 4 (31)
12
16/20/25
5V
0.6
20
CTM4 (8)
up 6 (47)
12
TouCAN
16/20/25
5V
0.6
20.97
68360
CPU32+
8/16/32
32
Yes
BDM/JTAG
68VZ328
FLX68000
8/16
24/32MB DRAM
2xSMC
Yes
2.5K
2x
EDO, FP, SD
4xSCC
1xSCP
2 ch
4x16, 2x32
3
8
opt. Ethernet
25/33
3.3 or 5V
0.3-1.0
25
ICE
2x
2x+2xPWM
10 (78)
8
LCD, RTC
up 33
2.7-3.3
0.06-0.1
33
29
68332 Microcontroller
AE0B36APO Computer Architectures
30
System Integration Module (SIM)
●
●
●
●
●
●
●
Interconnects intermodule buss and external bus
Includes support for programmable chip selects
generators
Ensures system protection/recovery from error states
SIM provides software watchdog monitor and a periodic
interrupt timer to support execution of time-critical control
routines.
It monitors system clock source frequency and system
bus.
The system clock can be based on 32.768-kHz crystal to
achieve low power consumption.
The module includes factory test and debugging
hardware
AE0B36APO Computer Architectures
31
Central Processing Unit (CPU)
●
32-bit architecture
●
Compatible with MC68000 and MC68010 processors
●
New instructions for embedded and control applications
●
●
●
●
●
Virtual memory support only with external MMU (Memory
Management Unit)
Accelerated processing of the loop including single
instruction
Instructions for table processing and interpolation
Exceptions processing extended to support embedded
applications
Provides tracing support with program flow change
detection (return, subroutine call, ... )
External HW breakpoint input and complete support for in32
system debugging – Background Debug Mode
●
AE0B36APO
Computer Architectures
Time Processor Unit (TPU)
AE0B36APO Computer Architectures
33
Time Processor Unit (TPU)
●
●
●
Dedicated micro-engine operating independently of the
CPU32
16 independent programmable channels and pins
Each channel has an event register consisting of a 16-bit
capture register, a 16-bit compare register and a 16-bit
comparator
●
Any channel can perform any time function
●
Each channel has six or eight 16-bit parameter registers
●
Each timer function may be assigned to more than one
channel
●
Two timer counter registers with programmable prescalers
●
Each channel can be synchronized to one or both counters
Computerchannel
Architectures priority levels
Selectable
●AE0B36APO
34
68376 Microcontroller
AE0B36APO Computer Architectures
35
Questions?
AE0B36APO Computer Architectures
36