Transcript 13.2 Analysis by Signal Tracing and Timing Charts
Unit 13 Analysis of Clocked Sequential Circuits
Ku-Yaw Chang [email protected]
Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University
Outline
13.1 A Sequential Parity Checker
13.2 Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits 2004/05/24 Analysis of Clocked Sequential Circuits 2
A Sequential Parity Checker A parity bit An extra bit Being added for purposes of error detection Odd parity Total number of 1 bits is odd Even parity Total number of 1 bits is even 2004/05/24 Analysis of Clocked Sequential Circuits 3
A Sequential Parity Checker A parity checker for serial data The data enters the circuit sequentially, one bit a time 2004/05/24 Analysis of Clocked Sequential Circuits 4
A Sequential Parity Checker A parity checker for serial data The data enters the circuit sequentially, one bit a time Z = 1 If the total number of 1 inputs received is odd Z = 0 If the total number of 1 inputs received is even An error occurs Data with odd parity Final output of Z = 0 2004/05/24 Analysis of Clocked Sequential Circuits 5
A Sequential Parity Checker The clock input To distinguish consecutive 0’s or consecutive 1’s on the X input 2004/05/24 Analysis of Clocked Sequential Circuits 6
State Graph for Parity Checker Two states are required S 0 an even number of 1’s received S 1 an odd number of 1’s received 2004/05/24 Analysis of Clocked Sequential Circuits 7
State Table for Parity Checker 2004/05/24 Analysis of Clocked Sequential Circuits 8
Parity Checker 2004/05/24 Analysis of Clocked Sequential Circuits 9
Outline 13.1 A Sequential Parity Checker
13.2 Analysis by Signal Tracing and Timing Charts
13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits 2004/05/24 Analysis of Clocked Sequential Circuits 10
Basic Procedure 1.
2.
3.
4.
5.
Assume an initial state of the flip-flops (all flip flops reset to 0 unless otherwise specified).
For the first input in the given sequence, determine the circuit output(s) and flip-flop inputs.
Determine the new set of flip-flop states after the next active clock edge.
Determine the output(s) that corresponds to the new states.
Repeat 2,3, and 4 for each input in the given sequence.
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Two Types of Clocked Sequential Circuits Moore machine the output of a sequential circuits is a function of the present state only Mealy machine the output is a function of both the present state and the input 2004/05/24 Analysis of Clocked Sequential Circuits 12
Moore and Mealy State Graphs 2004/05/24 Moore Analysis of Clocked Sequential Circuits Mealy 13
Moore Sequential Circuit Z is a function only of the present state Z = A B 2004/05/24 Analysis of Clocked Sequential Circuits 14
Moore Sequential Circuit Initially X = 0, A = B = 0
0 0
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0 1 0
Analysis of Clocked Sequential Circuits
0
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Moore Sequential Circuit Initially X = 0, A = B = 0
0 0 0 1 0 0 1 0
Analysis of Clocked Sequential Circuits
0
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Moore Sequential Circuit After the first active clock A = 1, B = 0, X = 1
1 0 0 1 0 1 1 1
Analysis of Clocked Sequential Circuits
1
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Moore Sequential Circuit After the first active clock Z =1, X = 1
1 0 1 0 1 1 1 1
Analysis of Clocked Sequential Circuits
1
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Moore Sequential Circuit After the second active clock A = 0, B = 1
0 1 1 0 1 1 0 0
Analysis of Clocked Sequential Circuits
1
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Moore Sequential Circuit After the second active clock Z = 1, X = 1
0 1 1 1 1 1 0 0
Analysis of Clocked Sequential Circuits
1
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Timing Chart 2004/05/24 Analysis of Clocked Sequential Circuits 21
Timing Chart Initial output Z = 0 could be ignored Not in response to any X input The output is displaced in time with respect to the input sequence.
X = 0 1 1 0 1 A = 0 1 0 1 0 1 B = 0 0 1 1 1 1 1 Z = (0) 1 1 0 1 0 2004/05/24 Analysis of Clocked Sequential Circuits 22
Mealy Sequential Circuit 2004/05/24 Analysis of Clocked Sequential Circuits 23
Mealy Sequential Circuit The output depends on both the input (X) and the flip-flops states (A and B), so Z may change either when the input changes or when the flip-flops change state.
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Mealy Sequential Circuit Initially
1 0 1 0
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1 1 0 1 0 1 1 1 1
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Mealy Sequential Circuit Initially
1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1
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Mealy Sequential Circuit First active clock
1 0 0 1
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1->0 0 0 1->0 1->0 0 1->0 1 1->0 0 0->1 1 1
Analysis of Clocked Sequential Circuits
0 1
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Mealy Sequential Circuit First active clock
1 0 0 1
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0 1->0 0 0 0 1->0 1->0 0 1->0 1 1->0 0 0->1 1 1
Analysis of Clocked Sequential Circuits
0 0->1
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Timing Chart 2004/05/24 Analysis of Clocked Sequential Circuits 29
False Outputs False Outputs After the circuit has changed state and before the input is changed, the output may temporarily assume an incorrect value.
Also called glitches and spikes X = 1 0 1 0 1.
A = 0 0 0 1 1 0 B = 0 1 1 1 1 0 Z = 1(0) 1 0(1) 0 1 2004/05/24 Analysis of Clocked Sequential Circuits 30