Slide 1

SOC Design Lecture 5

AMBA Signals


Slide 2

AMBA Bus Types

Kyungoh Park & Youpyo Hong, DGU


Slide 3

AMBA System Block Diagram


AMBA consists of Master, Slave,
Arbiter, Mux, and Decoder.



HADDR is the address from master to
slave.



HWDATA is the data from master to
slave.



HRDATA is the data from slave to
master.

Kyungoh Park & Youpyo Hong, DGU


Slide 4

Case of Data transaction


Single Master & Single Slave



Multi Master & Single Slave



Single Master & Multi Slave



Multi Master & Multi Slave
Kyungoh Park & Youpyo Hong, DGU


Slide 5

Single Master & Single Slave(SM&SS)

HCLK
HADDR

Master #1

HWRITE

Slave #1

HWDATA
HRDATA



A master can be directly connected to a slave. (No arbitration.)

Kyungoh Park & Youpyo Hong, DGU


Slide 6

SM SS Write and Read

HCLK
HADDR
HWRITE
HWDATA
HRDATA

Kyungoh Park & Youpyo Hong, DGU


Slide 7

HW #3
List all possible combinations of R/W for
SM SS situation.
 Which combinations violate AHB spec.?


Kyungoh Park & Youpyo Hong, DGU


Slide 8

Multi Master & Single Slave(MM & SS)
Master Selection

HWDATA

HCLK

Master #1

HADDR

HWDATA

HWRITE

HADDR
HWRITE

Slave #1

HWDATA

Master #2

HADDR
HRDATA
HWRITE




Multiple masters cannot access the same slave together.
So, there must be a way to arbitrate them.
Kyungoh Park & Youpyo Hong, DGU


Slide 9

Arbiter & HREADY
HGRANT #1

HREQUEST #1
HREQUEST #2

Arbiter
HGRANT #2

HCLK

Master
Selection

Master #1

HWDATA
HADDR
HWRITE

HWDATA
HADDR
HWRITE

Slave #1
Master #2

HWDATA
HADDR

HRDATA

HREADY

HWRITE






Arbiter decides which master takes the bus.
HREQUEST#x is a signal from Master#x to arbiter to try to use the bus.
HGRANT#x is a signal from arbiter to Master#x to allow the master to use the bus.
HREADY is a signal to the master indication the slave is ready for access.
Kyungoh Park & Youpyo Hong, DGU


Slide 10

Arbiter Timing





Is the Arbiter a combinational or sequential circuit?
Remember that the arbiter outputs are HGRANT#x and Master
Selection.
Consider the three cases.
1. Single master requests the bus. (No arbiter needed.)
2. Two masters request the bus simultaneously. (Comb. Arbiter
sounds OK.)
3. One master requests the bus while another master is using the
bus.
Kyungoh Park & Youpyo Hong, DGU


Slide 11

Data Transfer of MM & SS
CLK



HREQ.#1



HREQ.#2


HGRANT2#1

HGRANT#2

Mst. Sel.

Nothing

#1

HADDR#1

Nothing

#1

HADDR#2

HADDR

Nothing

Nothing

#1

Nothing

#2



Nothing

#2

Nothing

#2

Nothing




HGRANT는Combinational적으로 처리
해도 Delay는 그다지 크지 않을 것이다.
하지만, Master Selection의 경우는?
Master는 버스 사용 권한을 받은 후에야
전송을 개시한다. (Combinational적으로
처리는 가능하나 Delay가 꽤 길어질 것
이다.)
따라서, Mux가 입력값들을 Muxing 해야
하는 타이밍은 HGRANT 다음 사이클이
다.
그러므로, Master Selection은 순차회로
로 설계하는 것이 바람직하다.
그 밖의 이슈는 없는가?
Kyungoh Park & Youpyo Hong, DGU


Slide 12

SM & SS Reminder

HCLK
HADDR
HWRITE
HWDATA
HRDATA




HWDATA는 HADDR보다 1 사이클 늦게 들어온다.
따라서, HADDR과 HWDATA의 Muxing Timing은 다르다.
Kyungoh Park & Youpyo Hong, DGU


Slide 13

Data Transfer of MM & SS
CLK

HGRANT2#1

HGRANT#2

Mst. Sel.

Nothing

#1

#2

Nothing

HADDR

Nothing

#1

#2

Nothing

Mst. Sel.
For HWDATA
HWDATA




Nothing

#1

#2

Nothing

Nothing

#1

#2

Nothing

HWDATA의 Muxing을 위해, 1 사이클 더 늦은 Master Selection 신호가 필요하다.
더 이상의 이슈는 없는가?
Kyungoh Park & Youpyo Hong, DGU


Slide 14

Issue of HREADY
CLK

CLK

HGRANT2#1

HGRANT2#1

HGRANT#2

HGRANT#2

Mst. Sel.

Nothing

#1

#2

Nothing

Mst. Sel.

Nothing

#1

#2

Nothing

HADDR

Nothing

#1

#2

Nothing

HADDR

Nothing

#1

#2

Nothing

Mst. Sel.
For HWDATA
HWDATA

HREADY





Nothing

#1

#2

Nothing

Nothing

#1

#2

Nothing

Mst. Sel.
For HWDATA
HWDATA

Nothing

#1

#2

Nothing

Nothing

#1

#2

Nothing

HREADY

If a slave is not ready, it sends out hready low as above.
Find out the problems from the above timing diagrams? HW #4.
Kyungoh Park & Youpyo Hong, DGU