THE A-TEAM MATHIVATHANI BARATHI MOHAN DINESH UDAYAKUMAR BHARGAV BHAT BHASKAR SERVER SOFTWARE CLIENT SERVER HARDWARE CLIENT STOCK MARKET SCENARIO SERVER A COMPANY SOFTWARE CLIENT BUYER 1 SERVER B COMPANY HARDWARE CLIENT BUYER 2
Download ReportTranscript THE A-TEAM MATHIVATHANI BARATHI MOHAN DINESH UDAYAKUMAR BHARGAV BHAT BHASKAR SERVER SOFTWARE CLIENT SERVER HARDWARE CLIENT STOCK MARKET SCENARIO SERVER A COMPANY SOFTWARE CLIENT BUYER 1 SERVER B COMPANY HARDWARE CLIENT BUYER 2
Slide 1
THE A-TEAM
MATHIVATHANI BARATHI MOHAN
DINESH UDAYAKUMAR
BHARGAV BHAT BHASKAR
Slide 2
Slide 3
Slide 4
SERVER
1
SOFTWARE
CLIENT
1
SERVER
2
HARDWARE
CLIENT
2
Slide 5
STOCK MARKET
SCENARIO
SERVER A
COMPANY
1
SOFTWARE
CLIENT
BUYER 1
1
SERVER B
COMPANY
2
HARDWARE
CLIENT
BUYER 2
2
Slide 6
STOCK MARKET
SCENARIO
COMPANY A
COMPANY B
CUSTOM NETWORK
PROCESSOR
BUYER 1
BUYER 2
PAIRS TRADING
ALGORITHM
Slide 7
Incoming Packets
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
Input Arbiter
Output Port Lookup
Custom Network
Processor
Output Queues
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
Slide 8
Branch
Jump
PC
Branch Address
PC+1
INCOMING
PACKETS FROM
OUTPUT PORT
LOOKUP
Jump Address
Thread
Scheduler
FALL THROUGH
FIFO
Control
Unit
REGISTER
FILE 1
REG_SEL
INSTRUCTION
MEMORY 1
INSTRUCTION
MEMORY 2
OUT_FIFO
ALU
FIFO/DATA
MEMORY
MemToReg
ALUSrcB
Crypto
Engine
REGISTER
FILE 2
ALU Ctrl
Memory
Ctrl
Start_write
Start_proc
Start_read
Slide 9
Branch
Src.Port
Length
0001
XXXX
XXXXXXXX
0010
XXXX
XXXXXXXX
INCOMING
PACKETS FROM
OUTPUT PORT
LOOKUP
Jump Address
Thread
Scheduler
100
REG_SEL
INSTR 1
INSTR 2
User
Authentication
Module
FALL THROUGH
FIFO
Control
Unit
ALU
Invalid
PC+1
Valid
Jump
PC
Branch Address
Dst.Port
HW
ACC.
Packet Header
FIFO/Data Mem
ALUSrcB
Crypto
Engine
Scratch Mem
INSTR 3
INSTR 4
n0 port addr
n1 port addr
n0 val
n1 val
ALU Ctrl
Memory
Ctrl
OUT_FIFO
Start_write
Start_proc
Start_read
MemToReg
Slide 10
Latency Comparison – Hardware Vs Software
Routers
Custom Network Processor
SDN
1.8
1.6
Time in ms
1.4
1.2
1
0.8
0.6
0.4
0.2
0
32
64
128
256
No of Bytes per packet
512
1024
Slide 11
Date
Tasks
Status
6th April
Multithreaded Processor
Completed
13th April
Analysis of packet contents
Completed
20th April
Software Router Design
Completed
27th April
Mimicking Pairs Trading Algorithm
Completed
27th April
Implementation of User Authentication
In Progress
27th April
Implementation of Rerouting mechanism
In Progress
Analysis of achieved results
Yet to start
Slide 12
THE A-TEAM
MATHIVATHANI BARATHI MOHAN
DINESH UDAYAKUMAR
BHARGAV BHAT BHASKAR
Slide 2
Slide 3
Slide 4
SERVER
1
SOFTWARE
CLIENT
1
SERVER
2
HARDWARE
CLIENT
2
Slide 5
STOCK MARKET
SCENARIO
SERVER A
COMPANY
1
SOFTWARE
CLIENT
BUYER 1
1
SERVER B
COMPANY
2
HARDWARE
CLIENT
BUYER 2
2
Slide 6
STOCK MARKET
SCENARIO
COMPANY A
COMPANY B
CUSTOM NETWORK
PROCESSOR
BUYER 1
BUYER 2
PAIRS TRADING
ALGORITHM
Slide 7
Incoming Packets
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
Input Arbiter
Output Port Lookup
Custom Network
Processor
Output Queues
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
Slide 8
Branch
Jump
PC
Branch Address
PC+1
INCOMING
PACKETS FROM
OUTPUT PORT
LOOKUP
Jump Address
Thread
Scheduler
FALL THROUGH
FIFO
Control
Unit
REGISTER
FILE 1
REG_SEL
INSTRUCTION
MEMORY 1
INSTRUCTION
MEMORY 2
OUT_FIFO
ALU
FIFO/DATA
MEMORY
MemToReg
ALUSrcB
Crypto
Engine
REGISTER
FILE 2
ALU Ctrl
Memory
Ctrl
Start_write
Start_proc
Start_read
Slide 9
Branch
Src.Port
Length
0001
XXXX
XXXXXXXX
0010
XXXX
XXXXXXXX
INCOMING
PACKETS FROM
OUTPUT PORT
LOOKUP
Jump Address
Thread
Scheduler
100
REG_SEL
INSTR 1
INSTR 2
User
Authentication
Module
FALL THROUGH
FIFO
Control
Unit
ALU
Invalid
PC+1
Valid
Jump
PC
Branch Address
Dst.Port
HW
ACC.
Packet Header
FIFO/Data Mem
ALUSrcB
Crypto
Engine
Scratch Mem
INSTR 3
INSTR 4
n0 port addr
n1 port addr
n0 val
n1 val
ALU Ctrl
Memory
Ctrl
OUT_FIFO
Start_write
Start_proc
Start_read
MemToReg
Slide 10
Latency Comparison – Hardware Vs Software
Routers
Custom Network Processor
SDN
1.8
1.6
Time in ms
1.4
1.2
1
0.8
0.6
0.4
0.2
0
32
64
128
256
No of Bytes per packet
512
1024
Slide 11
Date
Tasks
Status
6th April
Multithreaded Processor
Completed
13th April
Analysis of packet contents
Completed
20th April
Software Router Design
Completed
27th April
Mimicking Pairs Trading Algorithm
Completed
27th April
Implementation of User Authentication
In Progress
27th April
Implementation of Rerouting mechanism
In Progress
Analysis of achieved results
Yet to start
Slide 12