SOC Design Lecture 9 SRAM vs. NOR Flash SRAM vs. NOR Flash There are asynchronous SRAM and synchronous SRAM. Our SRAM controller is.
Download ReportTranscript SOC Design Lecture 9 SRAM vs. NOR Flash SRAM vs. NOR Flash There are asynchronous SRAM and synchronous SRAM. Our SRAM controller is.
Slide 1
SOC Design Lecture 9
SRAM vs. NOR Flash
Slide 2
SRAM vs. NOR Flash
There are asynchronous SRAM and synchronous SRAM.
Our SRAM controller is for synchronous SRAM.
Read/Write occurs on edges on clock signal.
NOR Flash is asynchronous.
Read/Write occurs on control and address signal transitions.
You have a synchronous SRAM controller.
How to control NOR flash using sync. SRAM controller?
Taehyun Kim & Youpyo Hong, DGU
Slide 3
How to control asynchronous memory?
CLK
ADDR
Read
Addr.
ADDR
Chip
Enable#
Chip
Enable#
Output
Enable#
Output
Enable#
Write
Enable#
Write
Enable#
Data_in
Data_in
Data_out
Data
Data_out
Read
Addr.
Data
Control and address signals transition on edges on clock signal.
So, sync. controller can handle asynchronous memory.
Taehyun Kim & Youpyo Hong, DGU
Slide 4
Read
CLK
CLK
ADDR
ADDR
Read
Addr.
Chip
Enable#
Chip
Enable#
Output
Enable#
Output
Enable#
Write
Enable#
Write
Enable#
Data_in
Data_in
Data_out
Data
SRAM
SRAM and NOR flash are same.
Read
Addr.
Data_out
Data
NOR
Taehyun Kim & Youpyo Hong, DGU
Slide 5
Write
NOR write is SRAM write plus alpha.
NOR Flash needs “Command” before input address and data.
CLK
ADDR
CLK
Write
Addr
ADDR
Chip
Enable#
Chip
Enable#
Output
Enable#
Output
Enable#
Write
Enable#
Write
Enable#
Command
1
Command
2
Command
3
Write
Addr
NOR Bus Cycle
Data_in
Write
Data
SRAM
Data_in
Command
1
Command
2
Command
3
Write
Data
NOR
Taehyun Kim & Youpyo Hong, DGU
Slide 6
NOR Flash Commands
You can find this info. from distributed datasheet page 10.
Taehyun Kim & Youpyo Hong, DGU
Slide 7
Write with Command
CLK
ADDR
h555
h2AA
h555
Write
Addr
h55
Write
Data
Chip
Enable#
Output
Enable#
Write
Enable#
NOR Bus Cycle
Data_in
hAA
h55
Write is done.
To read data just written, care must be taken.
Taehyun Kim & Youpyo Hong, DGU
Slide 8
Wait Time
CLK
ADDR
h555
h2AA
h555
Write
Addr
h55
Write
Data
h555
Chip
Enable#
Output
Enable#
Write
Enable#
NOR Bus Cycle
Data_in
hAA
h55
Write Wait Time
To complete write operation, NOR flash needs some time.
Write(Program) Wait Time is described in the datasheet page 18.
Taehyun Kim & Youpyo Hong, DGU
Slide 9
Write Issue
Write
Data
Data In
Data Out
Data Out
CE#
WE#
NOR Flash
OE#
Typically, a memory cell of NOR can be changed to 0 from 1 but not
vice versa.
For example, if data was 1010 and you try to write 0101 to the same
position the result is 0000.
In such case, NOR flash needs initialization.
Taehyun Kim & Youpyo Hong, DGU
Slide 10
Erase
In NOR Flash, initialization is called “Erase”.
NOR Flash has two erase modes.
We use simple “Chip Erase”.
Taehyun Kim & Youpyo Hong, DGU
Slide 11
Chip Erase
CLK
ADDR
h555
h2AA
h555
h555
h2AA
h555
h555
h80
hAA
h55
h10
hAA
Chip
Enable#
Output
Enable#
Write
Enable#
NOR Bus Cycle
Data_in
hAA
h55
Chip Erase Time
Chip erase is similar to write but it has more commands.
Chip erase has wait time, too.
Taehyun Kim & Youpyo Hong, DGU
SOC Design Lecture 9
SRAM vs. NOR Flash
Slide 2
SRAM vs. NOR Flash
There are asynchronous SRAM and synchronous SRAM.
Our SRAM controller is for synchronous SRAM.
Read/Write occurs on edges on clock signal.
NOR Flash is asynchronous.
Read/Write occurs on control and address signal transitions.
You have a synchronous SRAM controller.
How to control NOR flash using sync. SRAM controller?
Taehyun Kim & Youpyo Hong, DGU
Slide 3
How to control asynchronous memory?
CLK
ADDR
Read
Addr.
ADDR
Chip
Enable#
Chip
Enable#
Output
Enable#
Output
Enable#
Write
Enable#
Write
Enable#
Data_in
Data_in
Data_out
Data
Data_out
Read
Addr.
Data
Control and address signals transition on edges on clock signal.
So, sync. controller can handle asynchronous memory.
Taehyun Kim & Youpyo Hong, DGU
Slide 4
Read
CLK
CLK
ADDR
ADDR
Read
Addr.
Chip
Enable#
Chip
Enable#
Output
Enable#
Output
Enable#
Write
Enable#
Write
Enable#
Data_in
Data_in
Data_out
Data
SRAM
SRAM and NOR flash are same.
Read
Addr.
Data_out
Data
NOR
Taehyun Kim & Youpyo Hong, DGU
Slide 5
Write
NOR write is SRAM write plus alpha.
NOR Flash needs “Command” before input address and data.
CLK
ADDR
CLK
Write
Addr
ADDR
Chip
Enable#
Chip
Enable#
Output
Enable#
Output
Enable#
Write
Enable#
Write
Enable#
Command
1
Command
2
Command
3
Write
Addr
NOR Bus Cycle
Data_in
Write
Data
SRAM
Data_in
Command
1
Command
2
Command
3
Write
Data
NOR
Taehyun Kim & Youpyo Hong, DGU
Slide 6
NOR Flash Commands
You can find this info. from distributed datasheet page 10.
Taehyun Kim & Youpyo Hong, DGU
Slide 7
Write with Command
CLK
ADDR
h555
h2AA
h555
Write
Addr
h55
Write
Data
Chip
Enable#
Output
Enable#
Write
Enable#
NOR Bus Cycle
Data_in
hAA
h55
Write is done.
To read data just written, care must be taken.
Taehyun Kim & Youpyo Hong, DGU
Slide 8
Wait Time
CLK
ADDR
h555
h2AA
h555
Write
Addr
h55
Write
Data
h555
Chip
Enable#
Output
Enable#
Write
Enable#
NOR Bus Cycle
Data_in
hAA
h55
Write Wait Time
To complete write operation, NOR flash needs some time.
Write(Program) Wait Time is described in the datasheet page 18.
Taehyun Kim & Youpyo Hong, DGU
Slide 9
Write Issue
Write
Data
Data In
Data Out
Data Out
CE#
WE#
NOR Flash
OE#
Typically, a memory cell of NOR can be changed to 0 from 1 but not
vice versa.
For example, if data was 1010 and you try to write 0101 to the same
position the result is 0000.
In such case, NOR flash needs initialization.
Taehyun Kim & Youpyo Hong, DGU
Slide 10
Erase
In NOR Flash, initialization is called “Erase”.
NOR Flash has two erase modes.
We use simple “Chip Erase”.
Taehyun Kim & Youpyo Hong, DGU
Slide 11
Chip Erase
CLK
ADDR
h555
h2AA
h555
h555
h2AA
h555
h555
h80
hAA
h55
h10
hAA
Chip
Enable#
Output
Enable#
Write
Enable#
NOR Bus Cycle
Data_in
hAA
h55
Chip Erase Time
Chip erase is similar to write but it has more commands.
Chip erase has wait time, too.
Taehyun Kim & Youpyo Hong, DGU