Transcript An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting Techniques Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012 Big Picture Designing Building Blocks for Ultra-Low–Voltage/Power CMOS RF.

An Ultra-Low-Voltage CMOS Mixer Using
Switched-Transconductance
Current-Reuse
Dynamic-Threshold-Voltage Gain-Boosting
Techniques
Amir Hossein Masnadi and Shahriar Mirabbasi
IEEE NEWCAS, June 2012
Big Picture
Designing Building Blocks for Ultra-Low–Voltage/Power
CMOS RF Front-End for applications such as:
•
Biomedical Application
Above Picture : Smart Stents, SoC and MEMS lab, UBC
•
Low Power Wireless Communication
Outline
• Overview of Conventional Active Mixers
• Overview of techniques
– Stack Reduction, LO-Gm Separation
– Current-Reuse
– Dynamic Threshold
• Mixer Design
– Gm-Stage - Double Balanced Current Reuse Gilbert Structure
– LO -Stage - Switched Supply Voltage
• Post-Layout Simulation Results and Comparison
• Concluding remarks
3
Conventional Active Mixers
• Gilbert-Type Mixer (Current commutating)
Reduce the voltage
drop across the Load
Resistor to increase
M1 drain Voltage
Challenge of biasing
current source in
saturation for low supply
voltage (e.g. VDD < 1.5)
Limitations for Supply-Voltage:
– 3 stacked transistors  each transistor VDS is around VDD/3
• Considering Vth is around 0.4 V, minimum supply voltage is around 1.2 V
– To increase conversion gain (CG) one can increase load (CGαRL×)
• Penalty: more voltage drop across load  trade-off between VDD and CG
Power Consumption issue:
– Mixer core is always ON (For Biasing the transistors)
Even more
challenging
if IIP3 has to
be improved
Supply Voltage (V) – Year (1997-2012)
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1996
Roughly Reduction of
0.085 V/Year
y = -0.0853x + 172.44
y = 4E+51e-0.059x
•Bulk_Driven
and Folded
Methods
•Very Low CG
(1<CG<9)
Range of Threshold Voltage
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
Mixer Power (mW)– Year (1997-2012)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1996
y = -0.8847x + 1781
y = 1E+122e-0.139x
Roughly a reduction
of 0.88 mW/Year
(it is leveling off)
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
Design Bottlenecks
•
Stacked Architectures : For decreasing Supply Voltage we should reduce Number of transistor
Stacked stages , we have different methods , below we bring ONLY two of them :
– Bulk-Driven Method
• Low Conversion Gain (Mostly below 10)
• Constant Biasing Current
– Folded Gilbert Architecture
• Moderate Conversion Gain – Wide Band
• Constant Biasing Current
• Bulky Inductors
• Threshold Voltage : If decreases the headroom will increases, so it would be nice if we
have lower threshold Voltage
We can't find any significant publication for reducing threshold voltage in Mixers
Proposed Techniques for Ultra Low Voltage Mixer
1. Reducing Stacked Transistors by Switched Transconductance:
– LO-Stage and Gm-Stage can be separated by switching supply
voltage of Gm-Stage
VDD
VDD
Gm1
VRF
Gm.VRF
GND
RL
– Turn ON & Off Gm-Stage with LO  Save Power
RL
VIF
VDD
+LO
-LO
+LO
LO-Stage
VDD
-LO
Gm1
-VRF
RL
+VRF
GND
RL
VDD
+VRF
Gm-Stage
-LO
+VRF
+VIF
VDD
-VIF
VDD
VDD
(a)
VDD
VDD
-VRF
Gm2
GND
+LO
VDD
-VRF
Current Commutating Approach
Gm ON/OFF Approach
Proposed Techniques for Ultra-Low-Voltage Mixer
2. Choosing Gm-Stage, Maximizing Conversion Gain and Linearity:
Pick a proper Gm-Stage for High Conversion Gain (High output Gm)
and High Linearity  Current-Reuse technique
– Overal Gm = gmn+gmp
– Linearity will be improved
Total Gm=gmn
Total Gm=gmn+gmp
Current-Reuse is similar to Push-Pull Buffer
-LO
Switching Stage
• We should implement a switch between VDD and GND
A
VDD
– Different Options :
• Simple Digital Inverter
• High-speed comparator (compare LO with GND, requires low LO power)
DTMOS
Inverter
• Inverter with Dynamic Threshold-Voltage:
Reduce VTH of NMOS transistors by connecting inverter output to body of
NMOS (DTMOS)
VDD
VDD
LO
LO
A
B
CL
(a)
CL
(b)
Output voltage of the inverter with CL=1pF, PLO= −8 dBm, 2.45 GHz LO signal
and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b)
without DTMOS.
Proposed Building Block For ULV Mixer
+LO
Switching
Stage
VDD
M2
RL
Cd
VRF
VIF
Current
Reuse
Gm stage
M1
-LO
Proposed Double-Balanced Design
+LO
10K
VBP
DTMOS
Inverter
10K
10K
VBN
10K
B
VDD
M7
Differential
Current
Reuse1
Cd
+VRF
M1
NMOS
-
Vout
+
-VRF
M2
Differential
Current
Reuse2
Cd
RL
M5
NMOS
Cd
M6
PMOS
VDD
A
10K VBN
10K
+VRF
M8
+VIF
Cd
RL -VRF
M4
PMOS
-VIF
M3
DTMOS
Inverter
-LO
10K
VBP
10K
Post-Layout Simulation Results
Case 1 :
Sub
Threshold
Case 2 :
Sub
Threshold
Case 3 :
Super
Threshold
Case 4 :
Super
Threshold
Case 5 :
Super
Threshold
VDD (V)
VBN (V)
VBP (V)
PLO (dBm)
NF (dB)
CG (dB)
IIP3 (dBm)
0.35
0.35
0.00
-3.75
12.7
13
-3.08
0.4
0.40
0.00
-4.00
11.2
14.7
-5.54
0.5
0.47
0.00
- 4.1
10.56
15.8
-8.6
0.8
0.4
0.4
-6.6
12
15.2
-7.04
1.2
0.75
0.6
-7.5
11.1
17.3
-8.1
PDC (mW)
0.48
0.6
1.6
3.4
12
20
• IBM0.13-µm CMOS
• VTH≈ 0.42 V
Conversion Gain (dB)
15
10
5
0
-5
VDD=1.2
VDD=0.8
VDD=0.5
VDD=0.4
VDD=0.35
-10
-15
-10
-9
-8
-7
-6
-5
-4
PLO(dBm)
-3
-2
-1
0
Effect of Dynamic Threshold Technique
20
0
DTMOS
Inverter
-10
Standard
Inverter
Conversion Gain(dB)
10
-20
VDD=0.5
VDD=0.5
VDD=1.2
VDD=1.2
-30
-40
-10
-9
-8
-7
-6
-5
PLO(dBm)
-4
-3
With DTNMOS
Without DTNMOS
With DTNMOS
Without DTNMOS
-2
-1
0
Conversion Gain at Different Supply Voltages
15
VDD
from 0.4V to 0.2V
Conversion Gain(dB)
10
5
VDD=0.25Volt
0
-5
-10
-15
-5
-4.5
-4
-3.5
-3
PLO(dBm)
-2.5
-2
-1.5
-1
Parameters
LO-Gm Architecture
This Work* This Work*
Separated Separated
JSSC
Separated
RFIC
RFIC
Stacked Folded
MTT
Folded
MTT
Folded
LO-Gm Separation
Method
DTMOS
Inverter
DTMOS
Inverter
Conventional
Inverter
N/A
N/A
N/A
N/A
Gm-Stage
Current
Reuse
Current
Reuse
NMOS
NMOS
Current
Reuse
NMOS
RF (GHz)
IF (MHz)
PLO(dBm)
VDD(V)
2.5
50
−3.75
0.35
2.5
50
−4.1
0.5
2.01
10
−4
1
2.4
60
−9
1
Curren
t
Reuse
2.4
1
−2.0
1.8
5.3
1
−3.6
0.9
8.6
4350
−3.3
0.6
0.5
18.3
−9
15.7
0.13
8.1
12.9
1
15.7
0.13
6.6
24
−11.6
8.9
0.13
0.6
15.9
−8
6
0.13
22.15/
21.36
14.41
/
16.17
1.75 /
0.50
24.32
/21.31
Subthresho
Subthreshold
ld
PDC(mW)
NF (dB)
IIP3(dBm)
Conversion Gain (dB)
CMOS Technology (µm)
FOM1 / FOM2
0.48
12.7
−3.08
13
0.13
31.65 /
26.3
1.6
10.56
−8.6
15.8
0.13
0.5
23.7
7
9.8
0.18
25.78 / 22 18.62 / 17.83
Concluding Remarks
Techniques to improve mixer performance:
•Reduce stacked levels
• For Gm-Stage , try to choose blocks with higher output Gm and Linearity
• Reduce VTH by body effect (Dynamic Threshold Technique), Both for Gm-Stage
and LO-Stage, so we can use it for increasing headroom an
• Turn-off circuit when you don’t want to use it to save power
TSMC 90nm Process
RF
VDD (V)
0.3
PLO (dBm)
-8.4
CG (dB)
27-15
Frequenc DC-12GHz
y
PDC (mW)
0.09
mWatt
LO
IF+
Active Balun
IF-
Resonator
Mixer Core
Resonator
Buffer
Acknowledgments
1. NSERC
2. CMC Microsystems
• IBM
• TSMC
And thank you for listening!
19
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