Low-Frequency Harmonic Reduction in Single-Phase Power Supply Systems Javier Sebastián Universidad de Oviedo Spain CIEP’98-1 Focusing the presentation Line • Single-Phase {• Power { Converter Three-Phase • High power Energy • Low power (110-220V, Philosophy { { { • Ac-to-dc • Ac-to-ac • Recovery.

Download Report

Transcript Low-Frequency Harmonic Reduction in Single-Phase Power Supply Systems Javier Sebastián Universidad de Oviedo Spain CIEP’98-1 Focusing the presentation Line • Single-Phase {• Power { Converter Three-Phase • High power Energy • Low power (110-220V, Philosophy { { { • Ac-to-dc • Ac-to-ac • Recovery. 

Low-Frequency Harmonic
Reduction in Single-Phase
Power Supply Systems
Javier Sebastián
Universidad de Oviedo
Spain
CIEP’98-1
Focusing the presentation
Line
• Single-Phase
{•
Power
{
Converter
Three-Phase
• High power
Energy
• Low power
(110-220V, <16A)
Philosophy
{
{
{
• Ac-to-dc
• Ac-to-ac
• Recovery to line
• No recovery
• Modifying conv. topology
• External connection
CIEP’98-2
Power Factor (PF) and Total
Harmonic Distortion (THD)
PF=
Input power
Input voltage, rms X Input current, rms
(Input current, rms)2 - ( Its 1ST harmonic, rms)2
THD=
Its 1ST harmonic, rms
CIEP’98-3
Questions (Q) & Answers (A):
• Q: Actually, are PF and THD the most important
parameter from the point of view of regulations?
• A: No, they are not
• Q: What do regulations say about PF and THD?
• A: Almost NOTHING. They only speak about the
maximum value of each harmonic
• Q: Frequently, what is the most usual objective
designing?
• A: To comply with regulations at as a low cost as
possible. Neither PF=1 nor THD=0 are the main
objectives
CIEP’98-4
Suggestion: to change words
and concepts
Power Factor Correction
Low-Frequency Harmonic Reduction
Objectives: •To comply with regulations
•Low efficiency penalty
•Low cost penalty
CIEP’98-5
Yes
Balanced
3 equipment?
Class
A
IEC 1000-3-2
No
Portable
tool?
Yes
Class
B
No
Lighting
equipment?
igpeak
Yes
Class
C
35%
/3
No
Especial
Waveform &
P<600 W?
No
Yes
Motor driven,
 control?
Yes
/3
/3
Clase D Template
No
Class
D
CIEP’98-6
Special wave shape for Class
D equipement
igpeak
35%
/3
/3
/3
“Each half cycle of
input current is
within the envelope
for at least 95% of
the time; peak of
current coincides
with center line”
CIEP’98-7
IEC 1000-3-2: Harmonics limits
n
3
Class A Class B Class C Class D
(A rms) (A rms) (% fun.) (mA/W)
2.3
3.45
30PF
3.4
5
1.14
1.71
10
1.9
7
0.77
1.155
7
1.0
9
0.40
0.60
5
0.5
2
1.08
1.62
2
-
4
0.43
0.645
-
-
6
0.30
0.45
-
-
8<n<40
1.84/n
2.76/n
-
CIEP’98-8
Type of solutions
Input current waveform
passive
non-sinusoidal
passive &
sinusoidal
passive &
non-sinusoidal
active
Devices
sinusoidal
active &
sinusoidal
active &
non-sinusoidal
CIEP’98-9
Passive solutions Active solutions
Robust & reliable
Cost effective
Low power
No preregulation
High weight & big size
Start-up problems
Medium quality of input
current *
Preregulation
Small size & low weight
No start-up problems
Either low & high power
High quality of input
current
*
More expensive
Less robust & reliable
* It depends on the input current goal
CIEP’98-10
Sinusoidal input
current
Ideal operation
Universal compliance
High power
Expensive
Useless at 50-60Hz if
passive
Lower efficiency
Non-sinusoidal
input current
Higher efficiency
Cheaper
Either passive or
active
Compliance
depending on regul.
Low power
CIEP’98-11
Type of solutions
Input current waveform
passive
non-sinusoidal
passive &
sinusoidal
passive &
non-sinusoidal
active
Devices
sinusoidal
active &
sinusoidal
active &
non-sinusoidal
CIEP’98-12
Series-resonant tank
High PF, low THD
Very bulky elements
Useful at HF
(e.g. 20 kHz)
at 50-60Hz
Voltage
IB
Current
CR
LR
CB
VB
Either
dc-to-ac
or dc-to-dc
converter
CIEP’98-13
Design trade-off
Voltage
Current
Low Q
Voltage
Current
High Q
Q= Z/R
Z=(LR/CR)1/2
R=VB/IB
The higher Q is:
 The higher PF is
 The lower THD is
 The higher stresses
in devices are
 The bulkier the
inductor is
CIEP’98-14
Type of solutions
Input current waveform
passive
non-sinusoidal
passive &
sinusoidal
passive &
non-sinusoidal
active
Devices
sinusoidal
active &
sinusoidal
active &
non-sinusoidal
CIEP’98-15
LC input filter with dc-side
inductor (I)
Voltage
Current
• Up to 300W
• Design in Class D
• Different results if acside inductor
LF
CB
Either
dc-to-ac
or dc-to-dc
converter
CIEP’98-16
LC input filter with dc-side
inductor (II)
200W, 180-260V
igpeak
35%
/3 /3 /3
23.3mH, EI-62.5,
0.58lb, 1.1W (losses)
200W, 90-260V
23.3mH, EI-87, 1.57lb,
2.74W (losses)
Class D template
Current
CIEP’98-17
LCC input filter with dc-side
inductor & capacitor (I)
Voltage
Current
• Up to 300W
• Design in Class A
• Different results if acside inductor LF & CF
CF LF
CB
Either
dc-to-ac
or dc-to-dc
converter
CIEP’98-18
LCC input filter with dc-side
inductor & capacitor (II)
Designing for Class A operation
igpeak
35%
Class D
template
/3 /3 /3
Class D template
CIEP’98-19
Type of solutions
Input current waveform
passive
non-sinusoidal
passive &
sinusoidal
passive &
non-sinusoidal
active
Devices
sinusoidal
active &
sinusoidal
active &
non-sinusoidal
CIEP’98-20
Resistor Emulator concept
vg(t)
VO
ig(t)
IO
iO(t)
iO(t)
ig(t)
IO
Resistor
Emulator
vg(t)
VO
(dc-to-dc
converter)
pg(t)
pO(t)
PO
CIEP’98-21
Resistor Emulator’s properties (I)
vg(t)
vg(t)
m(t)=
VO
vg(t)
=
VO/ Vg
sin(t)
VOconst.
Resistor
Emulator
(dc-to-dc
converter)
VO
•The voltage conversion ratio m(t)
changes from VO/ Vg to infinity
CIEP’98-22
Resistor Emulator’s properties (II)
VO
R
r(t)=
=
iO(t)
2sin2(t)
Resistor
Emulator
(dc-to-dc
converter)
VO
IO
iO(t)
iO(t)
IO
VO
R=VO/IO
•The load resistance seen by the converter,
r(t), changes from R/2 to infinity
CIEP’98-23
Consequences of these properties
(examples) (I)
ig
VO From
property #1
vg
Buck working
Buck off
vg
VO
ig 
A Buck conv. cannot work as resistor emulator
CIEP’98-24
Consequences of these properties
(examples) (II)
•Series Resonant Converter (SRC) cannot be
used as Resistor Emulator (from property #1)
•Zero-Voltage-Switched Quasi Resonant
Converters (ZVS QRC) cannot be used as
Resistor Emulator (from property #2),
because they cannot operate at no load.
CIEP’98-25
Consequences of these properties
(examples) (III):
Study of the current conduction mode (I)
L
Vg
L
R
Standar
d
dc-to-dc
VO
M=VO/Vg
K(R)=2L/(RT)
K(R)>Kcrit(M)
K(R)<Kcrit(M)
vg(t)
Resistor
r(t)
Emulator
R VO
m(t)=VO/vg(t)
k[r(t)]=2L/[r(t)T]
CCM
DCM
Dc-to-dc
k[r(t)]>kcrit[m(t)]
k[r(t)]<kcrit[m(t)]
CCM
DCM
Ac-to-dc
CIEP’98-26
Consequences of these properties
(examples) (IV):
Study of the current conduction mode (II)
k[r(t)]>kcrit[m(t)]
k[r(t)]<kcrit[m(t)]
CCM
DCM
k’crit[m(t)]= kcrit[m(t)]/[2sin2(t)]
Kapparent(R)=2L/(RT)
Kapparent(R) >k’crit[m(t)]
Kapparent(R) <k’crit[m(t)]
CCM
DCM
CIEP’98-27
Consequences of these properties
(examples) (V):
Study of the current conduction mode (III)
Kapparent(R) >k’crit[m(t)]
Kapparent(R) <k’crit[m(t)]
CCM
DCM
max. of {k’crit[m(t)]} = k’crit max
min. of {k’crit[m(t)]} = k’crit min
ALWAYS CCM
Kapparent(R) > k’crit max
ALWAYS DCM
Kapparent(R) < k’crit min
CIEP’98-28
Consequences of these properties
(examples) (VI):
Study of the current conduction mode (IV)
ALWAYS CCM
Kapparent(R) > k’crit max
ALWAYS DCM
Kapparent(R) < k’crit min
vg(t)= Vg PEAK sin(t)
M=VO/Vg PEAK
K’crit max
K’crit min
Buck-Boost,
SEPIC, Cuk
1/(2M2)
1/(2M+1)2
Boost
1/(2M2)
(M-1)/(2M3)
CIEP’98-29
Control of Resistor Emulators (I)
Multiplier approach control (I)
dc-to-dc
converter
Input current fixed by the reference
CIEP’98-30
Control of Resistor Emulators (I)
Multiplier approach control (II)
dc-to-dc
converter
Input current sinusoidal & its
value fixed by the reference
CIEP’98-31
Control of Resistor Emulators (I)
Multiplier approach control (III)
dc-to-dc
converter
Low-pass
filter
Input current sinusoidal & its value fixed by
the voltage feedback loop
CIEP’98-32
Control of Resistor Emulators (II)
Voltage-follower approach control
dc-to-dc
converter
Filter
Bulk
Controller for
dc-to-dc conv.
Low-pass
filter
CIEP’98-33
Control of Resistor Emulators (III)
Multiplier vs. Voltage-Follower
Multiplier
Voltage-Follower
 Either low or high output-  No current sensor
impedance topologies

No multiplier
 Perfect PF & THD

Cheaper
 Lower losses in the
 Lower losses in the diode
transistor
 Only high output Current sensor
impedance topologies
 Multiplier

Sometimes THD
 More expensive
CIEP’98-34
Control of Resistor Emulators (IV)
Improving THD in some converters with
voltage-follower control
dc-to-dc
converter
New
block
Low-pass
filter
CIEP’98-35
Resistor emulator topologies (I)
One switch, no isolation (I)
Boost
Buck-boost
CIEP’98-36
Resistor emulator topologies (II)
One switch, no isolation (II)
SEPIC
Cuk
CIEP’98-37
Resistor emulator topologies (III)
Comparing basic topologies
stress in inductor at switch to
semic. the input
GND
VO/ Vg
Boost
Low
Yes
Yes
>1
galv.
isolation
(possibl.)
No
Protection
BuckBoost
High
No
No
<1, >1
Yes
Yes
SEPIC &
Cuk
High
Yes
Yes
<1, >1
Yes
Yes
No
CIEP’98-38
Resistor emulator topologies (IV)
•One switch
• Isolation
Flyback
SEPIC
Cuk
CIEP’98-39
Resistor emulator topologies (V)
Voltage-Follower control (I)
ig av
iL
iS
iL
iS
Buck-Boost
in DCM
ig av
ig av
Ideal Resistor
Emulator
CIEP’98-40
Resistor emulator topologies (VI)
Voltage-Follower control (II)
ig av
iL
iL
Boost in DCM,
fS=const.
ig av
ig av
Non-ideal Resistor
Emulator
CIEP’98-41
Resistor emulator topologies (VII)
Voltage-Follower control (III)
ig av
iL
ig av
Boost in the
boundary
DCM/CCM
ig av
iL
ton toff
• ton const. each cycle
• toff depends on vg=(t)
• Therefore, fS=variable
Ideal Resistor
Emulator
CIEP’98-42
Resistor emulator topologies (VIII)
Voltage-Follower control (IV)
ig av
iL
iL
SEPIC &
Cuk in DCM
ig av
ig av
Ideal Resistor Emulator
(very low input current ripple)
CIEP’98-43
Resistor emulator topologies (IX)
Two switches, no isolation
Vg
VO
Buck
Boost=off
Buck=swt.
Boost=swt.
Buck=on
Boost
Vg
VO
CIEP’98-44
Resistor emulator topologies (X)
Two switches, isolation
To avoid starting-up &
stopping problems
Current-Fed Push-Pull
CIEP’98-45
Resistor emulator topologies (XI)
High-frequency topologies (I)
Resonant
 Integration of parasitics
 Only one switch
 Either ZCS or ZVS
 High output impedance
(voltage-follower control)
 Higher stress (conduction
losses)
 Frequency modulation
Soft-switching
PWM
Stress similar to PWM
Constant frequency
Either ZCS or ZVS
Several switches
Complex controller
CIEP’98-46
Resistor emulator topologies (XII)
High-frequency topologies (II): parasitic
integration
LR
CR
CB
ZCS-QR
SEPIC
C’R
LR
CB
Transformer
Diode
CIEP’98-47
Resistor emulator topologies (XIII)
High-frequency topologies (III): parasitic
integration
PRC
C’R
LR
Transformer
Diodes
Switches
CIEP’98-48
Resistor emulator topologies (XIV)
High-frequency topologies (IV):
voltage-follower control in resonant converters
Voltage
Current
ZCS-QR SEPIC
Voltage
Current
PRC
CIEP’98-49
Resistor emulator topologies (XV)
High-frequency topologies (V): Zero Voltage
Transition topologies
Main diode
CS
CR
CD
LR
CB
Main switch
Aux. devices
ZVT Boost
CIEP’98-50
Resistor emulator topologies (XVI)
High-frequency topologies (VI): Zero Voltage
Transition in IGBT using a MOSFET
Saux
CB
S1 S2
Aux. switch
Main
switches
S1
S2
Saux
Current-fed Push-Pull
CIEP’98-51
Dynamic problems in Resistor
Emulators
With multiplier approach control
dc-to-dc
converter
sin
Low-pass
filter
Same case with
Voltage-Follower
High gain at
100-120Hz
10dB lower
20dB lower
Input current
for different filters
CIEP’98-52
PFC based on an one-stage
Resistor Emulator
voltage
voltage
Cheap
Efficient
Resis.
Emul.
power
power
LOSSES
Poor dynamics
Big bulk
capacitor
CIEP’98-53
Fast-response topologies
•Two stages in cascade
•Topologies with
double powerprocessing
•Two-stage integrated
topologies
•Topologies with power
processing lower than
double
•“Charge Pump” or “LineVoltage Augmentation”
type
•Parallel PFC’s
•Based on High-Efficient
Post-Regulators
CIEP’98-54
Two-stage PFC (I)
voltage
voltage
Resis.
Emul.
voltage
2nd S.
power
LOSSES
LOSSES
Good dynamics
Smaller bulk
capacitor*
Lower efficiency*
Expensive
* In comparison with one-stage Resistor Emulators
CIEP’98-55
Two-stage PFC (II)
Example
Resistor
Emulator (Boost)
Dc-to-dc converter (PhaseShifted Full Bridge)
CIEP’98-56
Two-stage integrated topologies (I)
voltage
voltage
voltage
Good dynamics
Smaller bulk
capacitor
Fast-PFC
power
Cheaper
High stress
Low efficiency
LOSSES
CIEP’98-57
Two-stage integrated topologies (II)
Resistor Emulator
(DCM Boost)
Dc-to-dc converter
(Either DCM or
CCM Flyback)
CIEP’98-58
Two-stage integrated topologies (III)
ig av
•DCM Boost + Flyback
•If Flyback in DCM, lower
voltage variation across CB
ig av
•Quasi-sinusoidal input
current
High voltage & current
stress in the transistor
CIEP’98-59
Two-stage integrated topologies (IV)
ig av
ig av
•DCM SEPIC + Flyback
•If Flyback in DCM, lower voltage variation
across CB (even no variation)
•Sinusoidal input current
 High current stress in the transistor
CIEP’98-60
Two-stage integrated topologies (V)
Boost Integrated with Flyback Rectifier/Energy
storage/Dc-to-dc converter (BIFRED)
ig av
ig av
•Almost the same as
DCM Boost + Flyback
CIEP’98-61
Two-stage integrated topologies (VI)
Integrated Resistor Emulator + inverter
ig av
ig av
Fluorescent
Lamp
•DCM Boost Resistor Emulator + Half-Bridge
Parallel Resonant inverter
CIEP’98-62
“Charge Pump” or “Line-Voltage
Augmentation” type topologies (I)
voltage
voltage
voltage
Fast-PFC
power
Good dynamics
Small bulk capacitor
Higher efficiency
Complex
Double control
voltage
(for perfect input
current)
LOSSES
CIEP’98-63
“Charge Pump” type topologies (II)
vS(t)
pg(t)
pS(t)
pS(t) ig(t) 
VS(t)
ig(t) 
ig(t)
vS(t)
pg(t)
vg(t) 
VB
ig(t)  vS(t)
VB
dc-to-dc
or
dc-to-ac
converter
vg(t) 
pS(t)=0.27pg(t)
CIEP’98-64
“Charge Pump” type topologies (III)
Example:double Forward-Flyback
vS(t)
ig(t) 
ig(t) 
pg(t)
pS(t)
pS(t)>0.27pg(t)
vS(t)
VB
•vS(t) operates in DCM
•vS(t) controlled by FM
CIEP’98-65
“Charge Pump” type topologies (IV)
Example:Full-Bridge + FM PRC
pg(t)
pS(t)
vS(t)
ig(t) 
vS(t)
-
pS(t)>0.27pg(t)
+
VB/2
VB/2
FM PRC
Full Bridge
CIEP’98-66
Parallel PFC (PPFC) (I)
Input power
Power undergoing 2
transformations (32%)
Output
power
Power undergoing only
1 transformation (68%)
CIEP’98-67
Parallel PFC (PPFC) (II)
power
power
Good efficiency
 Several S
High stress S
Difficult design
aux
2nd stg.
aux
Main stg.
power
LOSSES
68%
and control
power
CIEP’98-68
PPFC (III): Example
CB
Forward
Current-fed Full Bridge
CIEP’98-69
High-Efficient Post-Regulators Concept
1.15·VBus - 0.87·VBus
VBus
High-Efficient
Post-Regulator
> 95%
Line
One-stage
PFC
No galvanic
isolation
PFC
CONTROLLER
LOW-PASS
FILTER
PWM
+
+
•Two-Output One-stage PFC + Two-Input Buck (TIBuck)
• Standard One-Stage PFC + Series-Switching PostRegulator (SSPR)
CIEP’98-70
High-Efficient Post-Regulators (I)
Two-Output Resistor Emulator + TwoInput Buck (TIBuck)
Line
Two-output
Resistor
Emulator
V1
V2
TIBuck
PWM
PFC
CONTROLLER
LOW-PASS
FILTER
Bus
+
+
POST-REGULATOR
CIEP’98-71
High-Efficient Post-Reg. (II): TIBuck
VO
V1
V1-V2
VO
V2
V2
VO-V2
V1-V2
V1-V2
VO-V2
V2
V2
V2
V2
V2IO undergoing no power processing,
(VO-V2)IO undergoing power processing
CIEP’98-72
Computing TIBuck’s efficiency
 TB 
HB
 HB
V2
1  (1   HB )
VO
 TB
is Buck Half-Converter
efficiency
is TIBuck
efficiency
TIBUCK EFFICIENCY
100
90%
85%
80
75%
 HB=50%
60
0.4
0.6
V2/VO
0.8
1
CIEP’98-73
High-Efficient Post-Regulators (III)
Power processing in a PFC based on a TIBuck
voltages
power
VO
P1
V1
V2
PO power
PO1
P2
P1
R.Em.
P2
PO1
V1
TIBuck
V2 85-90%
PO
PO
2
VO
PO
2
LOSSES
TB=99-97%
LOSSES
CIEP’98-74
High-Efficient Post-Regulators (IV)
Example: Two-output Flyback + TIBuck
V1=62V
V2=47V
R. Em.
PFC
CONTROLLER
LOW-PASS
FILTER
+
VO=54V
PWM
+
TIBuck
=85-82%, vg=85-264V rms
CIEP’98-75
High-Efficient Post-Regulators (V)
Series-Switching Post-Regulator (I)
VOC
One-stage
PFC
(Resistor
Emulator)
- +
+
VO
-
PWM
PFC
CONTROLLER
LOW-PASS
FILTER
Isolated
dc-to-dc
converter
+
+
VOSS
+
SSPR (non-isolated )
VOC<< VO
Pconv.<<PPFC
CIEP’98-76
Computing SSPR efficiency (I)
+
VO
SSPR
ss
VOSS= VO+ VOC
IO= IO1+ IO2
VOC·IO2
VO·IO1
-
+
PWM
IO2
+
Dc-to-dc
converter
C
IO1
-
C=
VOC
IO2
IO
VOSS
+
SSPR efficiency:
VOSS·IO2
1+KO
SS=
=
KO
VO·IO
1+ 
C
KO=VOC/VO
CIEP’98-77
Computing SSPR efficiency (II)
SS [%]
100
0.2
0.1
Voltages
95
Transient
response
90
85
KO=0.3
KO=VOC/VO
80
60
70
80
90
100
vOC
Steady state
ALWAYS
VOSS>VO
Conv. efficiency, c [%]
C=80%
KO=VOC/VO=0.1
vOSS
vO
Time
ss=97.7%
CIEP’98-78
High-Efficient Post-Regulators (VI)
Series-Switching Post-Regulator (II)
Power processing
voltage & power
vOSS
vOC vO
voltage
vOC
vO
DC/DC
R. Em.
85-90%
SSPR
power
LOSSES
LOSSES
vOSS
SSPR=97-98%
CIEP’98-79
High-Efficient Post-Regulators (VII)
Series-Switching Post-Regulator (III)
Same type
of converter
Dc-to-dc
converter
SSPR
Dynamic response
improves by using n+1
converters instead of n
Dc-to-dc
converter
Dc-to-dc
converter
Dc-to-dc
converter
n converters
One-stage
PFC
Dc-to-dc
converter
CIEP’98-80
High-Efficient Post-Regulators (VIII)
Series-Switching Post-Regulator (IV)
VOC=7V
-
+
+
*
VO=47V
+
VOSS=54V
-
-
*For discharging C
B
in short-circuit
Implementation based
on a Forward converter
CIEP’98-81
High-Efficient Post-Regulators (IX)
Setting voltages
Voltages
Transient response
v1
vO
v
Steady state
ALWAYS
V1>VO>V2
2
Time
A good trade-off:
V2 0.7-0.8V1
VO  (V1+V2)/2
SSPR
Transient
response
Voltages
TIBuck
vOSS
vO
Steady state
ALWAYS
VOSS>VO
Time
A good trade-off:
VO 0.7-0.8VOSS
CIEP’98-82
Topologies based on TIBuck (I)
Current-Fed
Push-Pull
TIBuck
CIEP’98-83
Topologies based on TIBuck (II)
2xBoost
TIBuck
CIEP’98-84
Topologies based on SSPR
Boos
t
Forward
SSPR
Flyback
Forward
SSPR
CIEP’98-85
PPFC versus 1 stg. PFC + SSPR
Forward
PPFC
Current-fed Full Bridge
Current-fed Full Bridge
1 stg. PFC + SSPR
Forward SSPR
CIEP’98-86
PPFC versus 1 stg. PFC + SSPR
Smaller capacitor
power
power
2nd stg.
power
Main stg.
power
68%
power
LOSSES
power
DC/DC
POC
POSS
1-stg.
PFC
85-90%
SSPR
LOSSES
POSS
Pd
LOSSES
POC
Pd
Higher %
Simpler control
CIEP’98-87
Type of solutions
Input current waveform
passive
non-sinusoidal
passive &
sinusoidal
passive &
non-sinusoidal
active
Devices
sinusoidal
active &
sinusoidal
active &
non-sinusoidal
CIEP’98-88
Example: Buck PFC
One switch, no isolation, slow response
ig
VO
vg
vg
Buck working
Buck off
vg
Always:
VO<Vg peak
VO
vg
ig
ig
No start-up problems
Low stress in devices
Slow transient
response
CIEP’98-89
Objectives for many new
converters
Small size Reactive elements at switching frequency
Cheap
Only one transistor & controller
Efficient
 Less than two power conversions
Always complying with the regulations (IEC 1000-3-2)
PF=1 & THD=0 is not the main worry!
CIEP’98-90
“Line-voltage augmentation” based
on an additional output in dcm
To help input
rectifier to start
conducting
Additional output in dcm
Line
vLine
iLine
Bulk
cap.
Conventional
dc-to-dc
converter
Load
CIEP’98-91
Additional output
in dcm
vLine
iLine
Example I
Bulk
cap.
Line
Filter
cap.
Flyback
vLine
iLine
Line
Filter
cap.
Bulk
cap.
Load
INTELEC’96
CIEP’98-92
Example II
Additional output in dcm
vLine
iLine
Line
INTELEC’96
2 Switch Forward
CIEP’98-93
Example III
DCM
Flyback
CB
Forward with additional DCM
Flyback-type output
CIEP’98-94
Characteristic
vO(is)
is
vLine
iLine
Line
Equivalent circuit with
additional output in dcm
v
(i
)
O
s
+
Non-linear
Loss-Free Resistor
dc-to-dc
is
Bulk
cap.
standard
converter
Load
Much energy re-cycled
High current stress (dcm)
Large variation in cap’s voltage
CIEP’98-95
Characteristic
vO(is)
is
vLine
is
Desired equivalent
circuit
v
(i
)
O
s
+
iLine
Line
Linear
Loss-Free Resistor
dc-to-dc
Bulk
cap.
standard
converter
Load
Less energy re-cycled
Lower current stress (ccm)
Smaller variation in cap’s voltage
CIEP’98-96
How can it be implemented?
Forward with LD and with L in ccm
iLD
D1
iO
L
LD
Vi
iL
Driver
VO
D2
Voltage across D2
1:1 : n
iL
Characteristic
{
{
VO=n·Vi·d - LD·fS·iO
VO=VS - RLF·iO
VS
vO(iO)
iO
iLD
td
iO
t=d/fS
1/fS
VS/RLF
CIEP’98-97
Forward with LD &
with L in ccm
vLine
Circuit
proposed
this year
(APEC’98)
LD
L
iLine
Line
Bulk
cap.
Filter
cap.
Flyback
vLine
iLine
L
LD
Load
Line
CIEP’98-98
Bulk
cap.
Active Input-Current Shaper (AICS)
VO(0)=VS
is
vO(is)
nS
n1
n2
VS can be
freely chosen
AIC
S
vO(is)
n1
AIC
S
With
extra tap
n2
Without
extra tap
VS depends on
the duty cycle
CIEP’98-99
Generalization of the AICS concept
AIC
S
Forward converter
(conventional)
AIC
S
Forward converter
with active clamp
CIEP’98-100
Designing the Active InputCurrent Shaper
VS(Vg,PO)
RLF
vg=Vgsint
vLine
C
VC(Vg,PO)
dc-to-dc P
O
converter
iLine
Vg min
VS min(Vg min , PO max)
VC(Vg,PO)
Vg max
RLF to minimize
re-cycled energy
C(Vg,PO)
PO max
CIEP’98-101
Determining “Class” and
compliance (IEC 1000-3-2)
Special wave shape
2.5%
2.5%
Class A: C>86.3º
compl. up to high
power levels (1kW)
C=86.3º
Boundary between
Class A & Class D
Class D: C<86.3º
compl. if
C>67.4º
CIEP’98-102
VS min= Vg min
d max=0.66
Vg max=1.2· Vg min
Design example 1
1

180º C
Input current
Vgmax,
Pmax
0.5
Vgmin,
Pmax
3
VC/Vg
Vgmin
Class A
2
120º
Vgmax
Vgmax,
Pmax/2
boundary
60º
1
Vgmax
Vgmin
Class D
0
Vgmin, Pmax/2
0
/3
2/3
Line angle

0
0º
0
0.5
1
Normalized power
High PF & low THD
High VC variation
0
0.5
1
Normalized power
CIEP’98-103
Design example 2
1 Input current
Vgmin,
Vgmax, Pmax
Pmax/2
0.5
180º
C
VS min= Vg min/2
d max=0.66
Vg max=1.4· Vg min
3
VC/Vg
Class A
Vgmin
120º
2
Vgmax
boundary
60º
1
Vgmax
0
Vgmin
Class D
0/3 /3
Line
angle

0º
0
0
0.5
1
Normalized power
Lower VC variation
Lower PF & higher THD
0
0.5
1
Normalized power
CIEP’98-104
Experimental results: prototype
Without extra tap
1.4mH
Line
430H
VC
Bulk
cap.
Output
Vg=190V-250V
VO=50V, IO=0.5-2A
fS=100kHz
CIEP’98-105
Efficiency in the prototype
94
270 V dc
92
90
As dc-to-dc converter
(voltage source across
the bulk capacitor)
355 V dc
310 V dc
25
75
50
Output Power [Watts]
100
190 V rms
88
As ac-to-dc converter
with Input-Current
Wave-Shaping.
3-7 points lower
250 V rms
84
220 V rms
80
25
50
75
Output Power [Watts]
100
CIEP’98-106
Input current waveforms &
harmonics
ENVELOPE
PO=100W
Current
0.43 A/div
0.5
Input current [A]
Current
0.87 A/div
Pinput=121 W
PF =0.845
THD=52%
0.4
0.3
0.2
IEC 1000-3-2
Measured
0.1
0
2 3
4
5
6
7
8
9 10 11 12 13 14
nth Harmonic
ENVELOPE
PO=50W
CIEP’98-107
Input current
(transformer with extra tap)
voltage
(100V/div)
voltage
(50V/div)
current
(0.67AV/div)
current
(0.67AV/div)
envelope
Class A
110V, 100W
Class D
220V, 100W
CIEP’98-108
AICS: Conclusions
•Main conventional topologies (no extra switches)
•Only 2 additional inductors and 2 additional diodes
•High-frequency filtered input current (ccm)
•Low “extra” stress (ccm & low capacitor voltage
change)
•Main converter either in ccm or dcm
•Trade-off between harmonics and re-cycled energy
(efficiency)
•Compliance with IEC 1000-3-2 with low efficiency
penalty
CIEP’98-109
Other types of “shapers”(I)
(APEC’97)
Either ccm or dcm.
If ccm, leakage inductance is needed
CIEP’98-110
Other types of “shapers”(II)
(Magnetic switch, INTELEC’95)
dcm
CIEP’98-111
Conclusions
•Passive, non-sinusoidal solutions are very
interesting for low-power applications.
•Topologies based on Resistor Emulators
need topological transformations in order to
improve dynamic response.
•Active, non-sinusoidal solutions are very
interesting from the point of view of cost.
This is a promising field for researching.
CIEP’98-112