Transcript Chapter 4 Instruction Level Parallelism

Princess Sumaya Univ.
Computer Engineering Dept.
Chapter 4:
22540 – Computer Arch. & Org (2)
Princess Sumaya University
Computer Engineering Dept.
CPU Operation Review
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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Computer Engineering Dept.
CPU Operation Review
ADD R3, R1, R2
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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CPU Operation Review
ADD R2, R1, +5
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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CPU Operation Review
LD R2, M[R1 + 5]
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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CPU Operation Review
ST M[R1 – 4], R2
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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CPU Operation Review
JMP + 3
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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CPU Operation Review
JE R1, R2, + 3
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Sel
A
Data
A
Data
B
Sel
B
Sel C
Memory
Shift
Left 2
0
M
U
X
1
Data C
Offset, Addr,
Immediate
Sign
Extend
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
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Pipelining
 Non Pipelined Process
P
C
Fetch Instr.
Get Operands
Execute
Store Result
Instr.
1
Instr.
1
Instr.
1
Instr.
1
ƮMem
ƮReg
ƮALU
ƮMem
Instr.
Mem.
Register
File
ALU
Data
Mem.
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Pipelining
 Non Pipelined Process
P
C
Fetch Instr.
Get Operands
Execute
Store Result
Instr.
2
Instr.
2
Instr.
2
Instr.
2
ƮMem
ƮReg
ƮALU
ƮMem
Instr.
Mem.
Register
File
ALU
Data
Mem.
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Pipelining
 Non Pipelined Process
● Clock Period =
● CPI (Clocks per Instruction) =
ƮMem
P
C
Instr.
Mem.
ƮReg
Register
File
ƮALU
ALU
ƮMem
Data
Mem.
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Pipelining
 Pipelined Process
Fetch Instr.
Get Operands
Execute
Store Result
Instr.
54321
Instr.
4321
Instr.
321
Instr.
21
ƮMem
ƮReg
ƮALU
ƮMem
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
R
e
s
u
l
t
Data
Mem.
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Pipelining
 Pipelined Process
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
Stage 2
Stage 3
R
e
s
u
l
t
Data
Mem.
Time
Stage 1
Stage 4
1
Fetch Instr. 1
2
Fetch Instr. 2
Get Operands 1
3
Fetch Instr. 3
Get Operands 2
Execute 1
4
Fetch Instr. 4
Get Operands 3
Execute 2
Store Result 1
5
Fetch Instr. 5
Get Operands 4
Execute 3
Store Result 2
6
Fetch Instr. 6
Get Operands 5
Execute 4
Store Result 3
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Pipelining
 Pipelined Process
● Clock Period =
● CPI =
ƮMem
ƮReg
ƮALU
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
ƮMem
R
e
s
u
l
t
Data
Mem.
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Pipelining Hazards
 Structural Hazards
Hardware can’t support instruction combination at a
certain time.
Example:
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
R
e
s
u
l
t
Data
Mem.
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Pipelining Hazards
 Data Hazards
One instruction has to wait for another to complete.
Example:
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
R
e
s
u
l
t
Data
Mem.
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Pipelining Hazards
 Data Hazards
One instruction has to wait for another to complete.
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
R
e
s
u
l
t
Data
Mem.
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Pipelining Hazards
 Data Hazards
One instruction has to wait for another to complete.
Forwarding:
ADD R3, R1, R2
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
R
e
s
u
l
t
Data
Mem.
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Pipelining Hazards
 Control Hazards
Decision depends on the result of unfinished instruction.
Example:
Time
Stage 1
1
Fetch Instr. 24
2
Fetch Instr. 28 Get Operands 24
?
?
3
4
Stage 2
Instr.
Mem.
I
R
Register
File
Execute 28
ALU
Y
Stage 4
Get Operands 28 Execute 24
X
P
C
Stage 3
R
e
s
u
l
t
Store Result 24
Data
Mem.
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Pipelining Hazards
 Control Hazards
Decision depends on the result of unfinished instruction.
● Stall
● Predict
● Delayed Branch
X
P
C
Instr.
Mem.
I
R
Register
File
ALU
Y
R
e
s
u
l
t
Data
Mem.
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Multiple Issue
 Multiple Instructions Execution (in single clock)
● CPI < 1 or IPC > 1.
● Static / Dynamic
● Speculation
Example:
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Static Multiple Issue
 Compiler Assisted
 Issue Packet
● Set of instructions issued in a given clock cycle.
● Simply, one large instruction with multiple operations.
 Very Long Instruction Word (VLIW)
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Single-Issue Datapath
4
+
Shift
Left
2
Register
File
Sel Data
A
A
0
1
2
Exception
Address
P
C
Instr.
Mem.
I
F
Sel Data
B
B
Sel
C
Data
C
Sign
Extend
I
D
0
1
+
A
L
U
E
X
ADDR
Data
S
T
0
Data
Mem.
Data
1
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Two-Issue Datapath
+
4
+
0
1
2
Exception
Address
P
C
Instr.
Mem.
I
F
Sel Data
A1 A1
Sel Data
B1 B1
Sel Data
A2 A2
Sel Data
B2 B2
Sel C1
Sel C2
Data C1
Data C2
0
1
0
1
A
L
U
Data
I
D
+
E
X
Data
Mem.
S
T
ADDR
Sign
Extend
Sign
Extend
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Two-Issue Datapath Example
 Two 32-bit instructions
ALU/JMP LD/ST
NOP Replacement
Example:
ALU/JMP
Loop:
LD/ST
LD R1, M[R2]
ADI R2, R2, – 4
ADD R1, R1, R3
JNE R2, 0, Loop
ST M[R2+4], R1
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Single-Issue Datapath Example
4
+
+
Register
File
0
1
P
C
Instr.
Mem.
2
I
F
Sel
A
Sel
B
Data
A
Data
B
Sel C
Data C
0
1
A
L
U
E
X
ADDR
Data
Data
Mem.
R1, M[R2]
R1, R1, R3
M[R2], R1
R2, R2, – 4
R2, 0, Loop
S
T
0
Data
Sign
Extend
Exception
Address
Loop: LD
ADD
ST
ADI
JNE
I
D
Clock
Fetch
Decode Execute Memory Store
1
LD
R1, M[R2]
2
3
4
5 ADD R1, R1, R3
1
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Single-Issue Datapath Example
Original Code:
Loop: LD
ADD
ST
ADI
JNE
R1, M[R2]
R1, R1, R3
M[R2], R1
R2, R2, – 4
R2, 0, Loop
Clock Fetch Decode Execute Memory Store
1
LD
2
R2
3
R2 + 0
4
M[R2]
5 ADD
R1
6
7
8
9
ST
10 ADI
11
12
13
14 JNE
15
16
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Single-Issue Datapath Example
Optimized Code:
Loop: LD
ADI
ADD
ST
JNE
R1, M[R2]
R2, R2, – 4
R1, R1, R3
M[R2+4], R1
R2, 0, Loop
Clock Fetch Decode Execute Memory Store
1
LD
2 ADI R2
3
R2 + 0
4
M[R2]
5 ADD
R1
6
7
8
9
ST
10 JNE
11
12
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Two-Issue Datapath Example
+
4
+
0
0
1
P
C
Instr.
Mem.
2
Exception
Address
I
F
Sel Data
A1 A1
Sel Data
B1 B1
Sel Data
A2 A2
Sel Data
B2 B2
Sel C1
Sel C2
Data C1
Data C2
1
0
1
I
D
A
L
U
Data
+
E
X
Data
Mem.
ADDR
S
T
Sign
Extend
Sign
Extend
ALU/JMP
Loop:
LD/ST
LD R1, M[R2]
ADI R2, R2, – 4
ADD R1, R1, R3
JNE R2, 0, Loop ST M[R2+4], R1
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Two-Issue Datapath Example
ALU/JMP
Loop:
LD/ST
LD R1, M[R2]
ADI R2, R2, – 4
ADD R1, R1, R3
JNE R2, 0, Loop ST M[R2+4], R1
Clock
Fetch
1
LD
2
ADI
3
4
5 ADD
6
7
8
9
JNE ST
10
11
12
Decode
Execute
Memory
Store
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Dynamic Multiple Issue
 Compiler Assisted (to move dependencies apart)
 Hardware Decided
● 0, 1 or more instructions issued in a given clock cycle.
 Superscalar Processors.
● Compiled code runs correctly independent of the issue
rate or pipeline structure.
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Dynamic Pipeline Scheduling
 Extension to Dynamic Multiple Issue
 Hardware Decided
● Choose which instruction to execute in a given clock cycle.
● Compiled code runs correctly independent of the issue
rate or pipeline structure
Example:
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Dynamic Pipeline Scheduling
 Instruction Fetch, Decode & Issue Unit
 Multiple Functional Units
 Commit Unit
Instruction
Fetch & Decode
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
Integer
Functional Unit
Integer
Functional Unit
Floating Point
Functional Unit
Floating Point
Functional Unit
Commit Unit
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Dynamic Pipeline Scheduling
 Out-of-Order (O-o-O) Execution
An operand may be in a register, reorder buffer or yet to be
produced by a functional unit.
 In-Order Issue
 In-Order Commit
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Speculative Execution
 Hardware-Based
● Branch Predictions
● Load Addresses
In-Order Commit
● Assures correctness in case of wrong prediction
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Out-of-Order Scheduling Scoreboard
 Scoreboarding (CDC 6600)
Pipeline:
Scoreboard
● IF
Floating Point Multiply
● IS
Floating Point Multiply
● RD
Floating Point Divide
● EX
● WB
Register
File
Floating Point Add
Integer Unit
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Out-of-Order Scheduling Scoreboard
 Scoreboarding (CDC 6600)
Pipeline:
● IF
● IS
Instruction Issue:
● RD
 If the functional unit is available.
● EX
 If no other active instruction has
the same destination register.
● WB

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Out-of-Order Scheduling Scoreboard
 Scoreboarding (CDC 6600)
Pipeline:
● IF
● IS
● RD
Read Operands:
● EX
 No previously issued instruction
has my operand as its destination.
● WB

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Out-of-Order Scheduling Scoreboard
 Scoreboarding (CDC 6600)
Pipeline:
● IF
Example:
● IS
● RD
● EX
● WB
Write Back Results:
 Stalls instructions which write
results to registers pending reads.

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Out-of-Order Scheduling Example
Example:
Wr Res
Exec
Rd Opr
Instruction
Issue
Instruction Status
Op
Unit
Busy
Functional Unit Status
Fi Fj Fk Qj Qk Rj Rk
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
ADD
F3, F1, 4
F.P Mul1
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add
MUL
F1, F5, F2
Integer
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
Register Result Status
F1
F2
F3
F4
F5
F6
•
•
•
F.U.
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add  + F3 F1 4
MUL
F1, F5, F2
Integer

Register Result Status
F1
F.U.
F2
F3
F4
F5
F6
•
•
•
Add
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1  × F5 F1 F2
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add  + F3 F1 4
MUL
F1, F5, F2
Integer
 
Register Result Status
F1
F.U.
F2
F3
F4
F5
Add
Add
Mul 1
F6
•
•
•
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1  × F5 F1 F2
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div  ÷ F6 F1 F3
DIV
F6, F1, F3
F.P. Add
MUL
F1, F5, F2
Integer
 
Add
Register Result Status
F1
F.U.
F2
F3
F4
F5
F6
Add
Add
Mul 1
Div
•
•
•
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div  ÷ F6 F1 F3
DIV
F6, F1, F3
F.P. Add  – F4 F2 5
MUL
F1, F5, F2
Integer
Add 

Register Result Status
F1
F.U.
F2
F3
F4
F5
F6
Add
Mul 1
Div
•
•
•
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1  × F1 F5 F2 Mul
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div  ÷ F6 F1 F3
DIV
F6, F1, F3
F.P. Add  – F4 F2 5
MUL
F1, F5, F2
Integer
Add  
 
Register Result Status
F1
F.U.
Mul 1
F2
F3
F4
Add
F5
F6
•
•
•
Div
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Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1  × F1 F5 F2 Mul
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add
MUL
F1, F5, F2
Integer

Register Result Status
F1
F.U.
Mul 1
F2
F3
F4
Add
F5
F6
•
•
•
Div
46 / 50
22540 – Computer Arch. & Org (2)
Princess Sumaya University
Computer Engineering Dept.
Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1  × F1 F5 F2 Mul
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add
MUL
F1, F5, F2
Integer

Register Result Status
F1
F.U.
F2
F3
F4
F5
F6
•
•
•
Mul 1
47 / 50
22540 – Computer Arch. & Org (2)
Princess Sumaya University
Computer Engineering Dept.
Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
ADD
F3, F1, 4
F.P Mul1  × F1 F5 F2 Mul
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add
MUL
F1, F5, F2
Integer
 
Register Result Status
F1
F.U.
F2
F3
F4
F5
F6
•
•
•
Mul 1
48 / 50
22540 – Computer Arch. & Org (2)
Princess Sumaya University
Computer Engineering Dept.
Out-of-Order Scheduling Example

IS
 RD  EX  WB
Wr Res
Exec
Instruction
Functional Unit Status
Rd Opr
Issue
Instruction Status
Unit
ADD
F3, F1, 4
F.P Mul1
SUB
F4, F2, 5
F.P Mul2
MUL
F5, F1, F2
F.P. Div
DIV
F6, F1, F3
F.P. Add
MUL
F1, F5, F2
Integer
Op
IF
Busy
Example:
Fi Fj Fk Qj Qk Rj Rk
Register Result Status
F1
F.U.
F2
F3
F4
F5
F6
•
•
•
Mul 1
49 / 50
Princess Sumaya University
22540 – Computer Arch. & Org (2)
Computer Engineering Dept.
Register Renaming
 Tomasulo’s Algorithm (IBM 360/91)
● Architectural Registers
● Physical (Hardware) Registers
● Dynamic Remap
Example:
50 / 50
Princess Sumaya University
Chapter 4
22540 – Computer Arch. & Org (2)
Computer Engineering Dept.
Princess Sumaya University
 Exercise 4.12
Exercise 4.13
 Exercise 4.14
 Exercise 4.16
Exercise 4.17
 Exercise 4.20
 Exercise 4.21
Exercise 4.22
 Exercise 4.23
22540 – Computer Arch. & Org (2)
Computer Engineering Dept.
 Exercise 4.25
Exercise 4.28
 Exercise 4.29
 Exercise 4.30
Exercise 4.31
 Exercise 4.32
 Exercise 4.33
Exercise 4.35
 Exercise 4.39