Transcript (1) Computer Engineering Dept.

Princess Sumaya Univ.
Computer Engineering Dept.
‫ بســام كحـالــه‬.‫د‬
Dr. Bassam Kahhaleh
Princess Sumaya Univ.
Computer Engineering Dept.
“Mano” Chapter 4:
Princess Sumaya University
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Micro-Operations
A micro-operation is an elementary operation,
performed during one clock pulse, on the information
stored in one or more registers.
R1 ← R1 + R2
CLK
CLK
LD1
Register 1
Register 2
R1
R1
22
R2
R2
33
5
Binary Adder
LD1
LD1
Adder
Adder
Adder
5
8
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Register Designation
 Whole register
Register
R1
 Portion of a register
 One bit in a register
Individual Bits
7 6 5 4 3 2 1 0
7
0
R1
Bit Numbering
Address
Data
Register Fields
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Parallel Register Transfer
CLK
 Unconditional
LD1
R1 ← R2
R1
 Conditional
P:
R1 ← R2
Control
Logic
 Simultaneous
5
2
P
Load
Register 1
Register 2
R1 ← R2 ,
R3 ← R2
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Bus Transfer
Register A
Register B
Register C
Register D
Register R3
Register R2
Register R1
Register R0
R2 ← RA
Consider:
R1 ← RD
Ri ← Rx
where
i = 0, 1, 2 or 3
x = A, B, C or D
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Bus Transfer
Register A
Register B
Register C
Register D
Register R2
Register R1
Register R0
4
4
Register R3
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Bus Transfer
Register A
Register B
Register C
Register D
4
Register A
4
Register B
Register C
4
4
Register D
4
4
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Bus Transfer
S3
Register A
Register B
Register C
Register D
A3 A2 A1 A0
B3 B2 B1 B0
C3 C2 C1 C0
D3 D2 D1 D0
S2
S1
S0
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Bus Transfer
Register A
Register B
Register C
Register D
4
Register A
4
Register B
Register C
4
4
Register D
4
MUX
4
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Bus Transfer
Register A
Register B
Register C
Register D
A3 A2 A1 A0
B3 B2 B1 B0
C3 C2 C1 C0
D3 D2 D1 D0
B3 C3 D3
B2 C2 D2
B1 C1 D1
B0 C0 D0
0
S1
S0
1
2
MUX
Y
3
0
S1
S0
1
2
MUX
Y
3
0
S1
S0
1
2
MUX
Y
3
0
S1
S0
1
2
3
MUX
Y
x
y
4 - bit Bus
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Bus Transfer
4
Register R3
Register R2
Ld
Register R1
Ld
z
w
Ld
Y3 Y2 Y1 Y0
I1
E
2x4
I0
Register R0
Ld
Enable
Decoder
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Micro-Operation Types
 Data Transfer
 Arithmetic Operations
 Logic Operations
 Shift Operations
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Micro-Operation Types
 Data Transfer
 Arithmetic Operations
S=A+B
 Logic Operations
 Shift Operations
A3
C4
B3
A2
B2
A1
B1
A0
A3
B0
FA
FA
FA
FA
S3
S2
S1
S0
B3
C0
A2
B2
A1
B1
A0
B0
C0
Binary Adder
C4
S3
S2
S1
S0
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Addition
S=A+B
A3
C4
B3
A2
B2
A1
B1
A0
A0
B0
FA
FA
FA
FA
S3
S2
S1
S0
C0
Cy

B0
Ci
S
Time (Propagation) delay = ?
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Addition
S=A+B
A3
t=0
C4
B3
A2
B2
A1
B1
A0
A0
B0
FA
FA
FA
FA
S3
S2
S1
S0
C0
Cy

B0
Ci
S
Time (Propagation) delay = ?
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Addition
S=A+B
A3
A2
B3
t=
C4
A1
B2
A0
A0
B1
B0
FA
FA
FA
FA
S3
S2
S1
S0
C0
Cy

B0
Ci
S
Time (Propagation) delay = ?
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Addition
S=A+B
A3
A2
B3
t = 2
C4
A1
B2
A0
A0
B1
B0
FA
FA
FA
FA
S3
S2
S1
S0
C0
Cy

B0
Ci
S
Time (Propagation) delay = ?
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Addition
S=A+B
A3
A2
B3
t = 3
C4
A1
B2
A0
A0
B1
B0
FA
FA
FA
FA
S3
S2
S1
S0
C0
Cy

B0
Ci
S
Time (Propagation) delay = ?
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Addition
S=A+B
A3
t = 4
C4
B3
A2
B2
A1
B1
A0
A0
B0
FA
FA
FA
FA
S3
S2
S1
S0
C0
Cy

B0
Ci
S
Time (Propagation) delay = 4 
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Addition
A←A+B
Load
E
A
Flag
B
Binary Adder
Cy
C0
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Subtraction
A←A⎯B _
A←A+ (B+1)
A3
B3
A2
B2
B
A1
B1
A0
B
0
B0
M
B
B
1
C4
FA
FA
FA
FA
S3
S2
S1
S0
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Increment
A←A+1
A3
A2
0
C4
A1
0
A0
0
0
FA
FA
FA
FA
S3
S2
S1
S0
1
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Decrement
A←A⎯1
A3
A2
1
C4
A1
1
A0
1
1
FA
FA
FA
FA
S3
S2
S1
S0
0
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Arithmetic
A3
A2
B3
B0
0 1
C2 C1 C0
0 1 2 3
MUX S1
S0
Y
0 1 2 3
MUX S1
S0
Y
0 1 2 3
MUX S1
S0
Y
0 1 2 3
MUX S1
S0
Y
A0
B1
0 1
0 1
0 1
C4
A1
B2
FA
FA
FA
FA
S3
S2
S1
S0
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Arithmetic
C2 C1 C0
A3
Function
0 0 0
Y=A+B
0 0 1
Y=A+B+1
0 1 0
Y=A+B
0 1 1
Y=A–B
1 0 0
Y=A
1 0 1
Y=A+1
1 1 0
Y=A–1
1 1 1
Y=A
B3
A2
0 1
A1
0 1
0 1 2 3
MUX S1
S0
Y
C4
B2
B1
A0
0 1
0 1 2 3
MUX S1
S0
Y
B0
0 1
0 1 2 3
MUX S1
S0
Y
C2 C1 C0
0 1 2 3
MUX S1
S0
Y
FA
FA
FA
FA
Y3
Y2
Y1
Y0
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Arithmetic
C2 C1 C0
Function
0 0 0
S=A+B
0 0 1
S=A+B+ 1
0 1 0
S=A+B
0 1 1
S=A–B
1 0 0
S=A
1 0 1
S=A+1
1 1 0
S=A–1
1 1 1
S=A
B
A
4
4
C2
C1
C0
Arithmetic Unit
4
S
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Arithmetic
Data
B
A
4
4
C2
C1
C0
Arithmetic Unit
4
S
Control
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Micro-Operation Types
 Data Transfer
 Arithmetic Operations
 Logic Operations
 Shift Operations
AND: S = A Λ B
OR: S = A V B
XOR: S = A  B
AND: S = A • B
OR: S = A + B
XOR: S = A  B
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Logic
Ai
0
Bi
1
2
MUX
Y
C1 C0
3
S1
S0
Fi
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Logic
A3
B3
A2
B2
A1
B1
A0
B0
C1 C0
0
1
2
MUX
Y
F3
3
0
S1
S0
1
2
MUX
Y
F2
3
0
S1
S0
1
2
MUX
Y
F1
3
0
S1
S0
1
2
MUX
Y
3
S1
S0
F0
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Logic
A3
C1 C0
B3
A2
B2
A1
B1
A0
B0
Function
0 0
F=AΛ B
0 1
F =A V B
1 0
F=A B
1 1
F=A
C1 C0
0
1
2
MUX
Y
F3
3
0
S1
S0
1
2
MUX
Y
F2
3
0
S1
S0
1
2
MUX
Y
F1
3
0
S1
S0
1
2
MUX
Y
3
S1
S0
F0
31 / 42
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Logic
A
C1 C0
4
Function
0 0
F=AΛ B
0 1
F=AV B
1 0
F=A B
1 1
F= A
B
C1
C0
4
Logic Unit
4
F
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Logic
Data
A
B
4
C1
C0
4
Logic Unit
4
F
Control
33 / 42
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Micro-Operation Types
 Data Transfer
 Arithmetic Operations
 Logic Operations
 Shift Operations
● Logical Shift
shl A
shr A
● Arithmetic Shift
ashl A
0
A7
A0
A7
A0
A7
ashr A
● Circular Shift
cil A
A7
A7
A6
A6
A0
0
0
A0
A0
cir A
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Logical & Arithmetic Shift
C1 C0
Function
0 0
F=A
0 1
F = shr A
1 0
F = shl A
1 1
F = ashr A
A3
A2
0
A3
A3
A1
A2
A0
A1
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
F3
F2
F1
F0
0
C1
C0
35 / 42
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Logical & Arithmetic Shift
C1 C0
Function
0 0
F=A
0 1
F = shr A
1 0
F = shl A
1 1
F = ashr A
A3
A2
0
A3
A3
A1
A2
A0
A1
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
F3
F2
F1
F0
0
0
0
36 / 42
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Logical & Arithmetic Shift
C1 C0
Function
0 0
F=A
0 1
F = shr A
1 0
F = shl A
1 1
F = ashr A
A3
A2
0
A3
A3
A1
A2
A0
A1
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
F3
F2
F1
F0
0
0
1
37 / 42
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Logical & Arithmetic Shift
C1 C0
Function
0 0
F=A
0 1
F = shr A
1 0
F = shl A
1 1
F = ashr A
A3
A2
0
A3
A3
A1
A2
A0
A1
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
F3
F2
F1
F0
0
1
0
38 / 42
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Logical & Arithmetic Shift
C1 C0
Function
0 0
F=A
0 1
F = shr A
1 0
F = shl A
1 1
F = ashr A
A3
A2
0
A3
A3
A1
A2
A0
A1
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
F3
F2
F1
F0
0
1
1
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Logical, Arithmetic, & Circular Shift
C2
Shift
0
Regular
A0
A3
A3
1
A2
A1
A0
Circular
A3
A3
A2
A1
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
0 1 2 3
MUX S1
Y S0
F3
F2
F1
F0
C2
C1
C0
40 / 42
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Logical, Arithmetic, & Circular Shift
C2 C1 C0
A
Function
x 0 0
F=A
0 0 1
F = shr A
0 1 0
F = shl A
0 1 1
F = ashr A
1 0 1
F = cir A
1 1 0
F = cil A
4
C2
C1
C0
Shifter
4
F
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Arithmetic and Logic Unit (ALU)
A
B
4
C0
C1
C2
4
Arithmetic Unit
Logic Unit
4
0
C3
S0
4
MUX
1
Y
4
C4
C5
C6
Shifter
4
Y
42 / 42
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Homework
Chapter 4
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
4-1
4-2
4-3
4-4
4-5
4-6
4-8
4-9
4-10
4-11
4-13
4-15
4-16
4-17
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Homework
 Mano
4-1
Show the block diagram of the hardware that implements
the following register transfer statement:
yT2:
R2 ← R1,
R1 ← R2
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Homework
4-2
The outputs of four registers, R0, R1, R2, and R3, are
connected through 4-to-1-line multiplexers to the inputs
of a fifth register, R5. Each register is eight bits long. The
required transfers are dictated by four timing variables
T0 through T3 as follows:
T0: R5 ← R0
T1: R5 ← R1
T2: R5 ← R2
T3: R5 ← R3
The timing variables are mutually exclusive, which means
that only one variable is equal to 1 at any given time,
while the other three are equal to 0. Draw a block
diagram showing the hardware implementation of the
register transfers. Include the connections necessary from
the four timing variables to the selection inputs of the
multiplexers and to the load input of register R5.
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Homework
4-3
Represent the following conditional control statement by
two register transfer statements with control functions.
If (P = 1) then (R1 ← R2) else if (Q = 1) then (R1 ← R3)
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Homework
4-4
What has to be done to the bus system of Fig. 4-3 to be
able to transfer information from any register to any
other register? Specifically, show the connections that
must be included to provide a path from the outputs of
register C to the inputs of register A.
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Homework
4-5
Draw a diagram of a bus system similar to the one shown
in Fig. 4-3, but use three-state buffers and a decoder
instead of the multiplexers.
4-6
A digital computer has a common bus system for 16
registers of 32 bits each.
The bus is constructed with multiplexers.
a. How many selection inputs are there in each
multiplexer?
b. What size of multiplexers is needed?
c. How many multiplexers are there in the bus?
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Homework
4-8
Draw the block diagram for the hardware that
implements the following statements:
x + yz:
AR ← AR + BR
where AR and BR are two n-bit registers and x, y, and z
are control variables. Include the logic gates for the
control function. (Remember that the symbol + designates
an OR operation in a control or Boolean function but that
it represents an arithmetic plus in a microoperation.)
4-9
Show the hardware that implements the following
statement. Include the logic gates for the control function
and a block diagram for the binary counter with a count
enable input.
xyT0 + T1 + y’T2:
AR ← AR + 1
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Homework
4-10 Consider the following register transfer statements for
two 4-bit registers R1 and R2.
xT:
Rl ← R1 + R2
x’T:
Rl ← R2
Every time that variable T = 1, either the content of R2 is
added to the content of R1 if x = 1, or the content of R2 is
transferred to R1 if x = 0. Draw a diagram showing the
hardware implementation of the two statements. Use
block diagrams for the two 4-bit registers, a 4-bit adder,
and a quadruple 2-to-1-line multiplexer that selects the
inputs to R1. In the diagram, show how the control
variables x and T select the inputs of the multiplexer and
the load input of register R1.
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Homework
4-11 Using a 4-bit counter with parallel load and a 4-bit adder,
draw a block diagram that shows how to implement the
following statements:
x:
R1 ← R1 + R2
x’y:
R1 ← R1 + 1
Add R2 to R1
Increment R1
4-13 Design a 4-bit combinational circuit decrementer using
four full-adder circuits.
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Homework
4-15 Design an arithmetic circuit with one selection variable S
and two n-bit data inputs A and B. The circuit generates
the following four arithmetic operations in conjunction
with the input carry Cin. Draw the logic diagram for the
first two stages.
S
Cin = 0
0 D = A + B (add)
1 D = A – 1 (decrement)
Cin = 1
D = A + 1 (increment)
D = A + B’ + 1 (subtract)
4-16 Derive a combinational circuit that selects and generates
any of the 16 logic functions listed in Table 4-5.
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Homework
4-17 Design a digital circuit that performs the four logic
operations of exclusive OR, exclusive-NOR, NOR, and
NAND. Use two selection variables. Show the logic
diagram of one typical stage.