Transcript BTW08-Presentation 4.1

Alfred L. Crouch
Chief Technologist & Director of IJTAG R&D
Vice-Chair IEEE P1687 “IJTAG” Working Group
P1687 2008 Update: The Whole Story
The IJTAG Features and Capabilities
BTW – Sept 2008
Crouch
The Current Committee
Active P1687 (IJTAG) Working Group






Chair: Ken Posse (Avago)
Vice Chair: Al Crouch (Asset-InterTech)
Editor: Jeff Rearick (AMD)
Std. Liaison: Ben Bennetts (Bennetts Assoc. – Ret)
Web Master: Michael Laisne’ (Qualcomm)
A Camel is a Horse
designed by committee…
Current Working Group Members:
 Jason Doege (AMD); Mike Ricchetti (ATI); Srinivas Patel, Mike Wiznerowicz (Intel);
Chip & Board Design
Basic Camel
 Bill Eklow, Hongshin Jun, Ted Eaton (Cisco); Thai-Minh Nguyen (LSI
 Songlin Zhuo (Qualcomm); Pradipta Ghosh (Broadcom);
External Instruments
 Hugh Wallace, Rick Nygard, Richard Dugan (Agilent); Scott Hartranft (Tektronix)
One Hump
 Thomas Rinderknecht, Paul Reuter (Mentor); J.F. Cote (LogicVision);
EDA Tool Providers
 Rohit Kapur (Synopsys) – 1450.6 CTL Liason; Ed Malloy (Cadence);
Two Hump
 Bill Tuthill (Intellitech); Stylianos Diamantidis (GlobeTech);
John Potter
(Asset-InterTech);
JTAG Tool
Providers
Three Hump
 Harrison Miles, Andrew Levy (Corelis); Heiko Ehrenberg (Goepel);
System Level Users
 Brad Van Treuren, Michele Portolan, Suresh Goyal (Alcatel-Lucent);
5-Legged Moose
We have broad representation, but it has slowed us down a little
Some Semantics…from the Corporate
Confusion Department…
 Lots of new and used Acronyms and Abbreviations:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IJTAG = Internal JTAG
BSDL Zone = Boundary Scan Description Language Zone
TDR = Test Data Register
IIF = Instrument Interface Register
GDR or GIR = Gateway Data or Gateway Instruction Register
SIB = Select Instrument Bit
MIB = Multiple-Input Bit
GWEN = Gateway Enable Instruction
HIP = Hierarchical Interface Port
HDL = Hardware Description Language
IDL = Instrument Description Language
CDL = Connectivity Description Language
PDL = Protocol Description Language
S/C/U = Shift/Capture/Update
Alfred L. Crouch
Chief Technologist & Director of IJTAG R&D
Vice-Chair IEEE P1687 “IJTAG” Working Group
P1687 2008 Update: The Whole Story – Part 1
The IJTAG Features and Capabilities
The Instrument and Hardware Portion
BTW – Sept 2008
Crouch
What is IJTAG? What are Instruments?

IJTAG is the P1687 Proposed Standard which will be designed to enable
more efficient access and optimized interconnect to embedded logic and
electrical/environmental monitors inside the chip:
•
•
•
for all purposes: functional configuration, test, debug-diagnosis, yield
for all environments: wafer probe, package test, die-stack, board test, in-system
to promote reuse from one environment to the next
•
P1687.0 will stipulate the 1149.1 JTAG port as the primary access mechanism
•
Embedded content is defined as instruments and includes items such as:

FCN: Bus Configuration, Pin Configuration, Power Modes, Clock Modes

DFT: MBIST, LBIST, Scan-Compression, Test-Wrappers, Clock-Controllers

DFD: Logic Analyzers, Bus Monitors, Traffic Monitors, Trace-Buffers, Hardware
Assertions, Embedded O-Scopes

DFY: Voltage Sensors, Temperature Sensors
•
The goal is to enable standard control and configuration (architectures, connections, and
interfaces) and to also:

allow higher bandwidth data delivery to instruments that need it

allow instrument-to-instrument communication

allow TAP-asynchronous instrument operations (e.g. a fail flag)
What Problem Does IJTAG Solve?
 IJTAG solves two main problems:
1. Specifying how to Include embedded logic not meant for board test under the
1149.1 TAP and TAP Controller without causing problems with 1149.1
Compliance
o
o
o
o
o
Clogging up the 1149.1 BSDL with non-board test content – higher probability of bad BSDL
Badly or inadequately describing complex instruments
Growing the Instruction Register with tens, hundreds, or even thousands of instructions
Dealing with one-hot instructions (instead of IR encoding)
Dealing with hierarchical nesting and changing scan-path lengths
2. Enabling optimization, efficiency, and tradeoffs to be applied to the growing
volume of embedded logic and electrical monitor content (instruments) in
modern chips
o
o
o
o
Allows a variety of connections instead of just JTAG daisy chain (all-at-once serial) or star (oneat-a-time)
Allows organization of embedded content into groups and hierarchies…
…enables reuse of IP that may have entire instrument architectures (as opposed to TAPs)
Offloads the non-board-test content out of the 1149.1 Instruction Register
Standard JTAG Flow-Through Model
1.
2.
3.
4.
TAP
TAP Controller
1.
SM
2.
IR
1.
Instructions
2.
Decode
3.
Bypass
4.
½ Cycle-Adj
Registers
BSDL
Boundary Scan Register (BSR)
ID-Code Register (IDC)
N Test Data Register (TDR)
Test
Access
Port
TDI
TDO
XTRST
TCK
Bypass Register (BYP)
Instruction Register (IR)
Z
Decode
TAP Controller
State-Machine[4]
TMS
Compliance
Enable
Today, 1 Instrument usually = 1 TDR + at least 1 JTAG Instruction
TAP State Machine
Test
Logic
Reset
1
0
Run
Test
Idle
0
1
Select
Data
Register
1
Select
Instruct
Register
1
0
1
Shift
Data
Register
Capture
Instruct
Register
1
0
0
Shift
Instruct
Register
1
Exit 1
Data
Register
0
Pause
Data
Register
1
0
1
Exit 2
Data
Register
0
1
Exit 1
Instruct
Register
1
0
0
Pause
Instruct
Register
1
Exit 2
Instruct
Register
0
1
1
Update
Data
Register
Update
Instruct
Register
1
0
Legal Sequences: those allowed by the
compliant 1149.1 TAP SM
1.
Normal Event Order: Capture-Shift-Update
2.
All State Changes on Rising-TCK & TMS
3.
Five 1’s on TMS goes to TLR from anywhere
in the State Machine
4.
All “Inputs and Samples” on Rising-TCK
5.
All “Outputs and Updates” on Falling-TCK
0
Capture
Data
Register
0
•
0
1
0
The IJTAG Differences
1149.1 JTAG Zone
TAP & TAP Controller
Small Instruction Register
All Items Described in BSDL
Keeps JTAG Logic Simple
and Compliant – only addition
is Instruction to small IR to
select Gateway Register
P1687 IJTAG Zone
Instruments
G
A Instrument Control Connections
T
Instrument Data Connections
E
W
All Items Described in “HDL/PDL”
A
Y
R
E
G
Allows complex instruments
to be described and to include
the extra information needed
that would complicate BSDL
The Gateway Register is a TDR-like structure existing in both sides
1149.1 Supports P1687 by…
 By including a TDR called a Gateway and an instruction
(GWEN: GateWay ENable) to select it in the 1149.1
Instruction Reg; to describe the Gateway in the BSDL
WSOi
WSIo
Gateway
Min Fixed Length &
Private for BSDL
All inside the box
described in the
1149.1 BSDL
IDCode
BSR
BYP
TDI
1149.1-IR
G
w
e
n
H
I
P
e
n
TDO
The Gateway Select-Instrument-Bit (SIB)
The Key Element for Adding, Organizing, Managing Embedded Content
TDO
Shift-Update Cell
used as a SIB
WSOi
WSIo
TDI
Sel_i
SC
U
The HIP
TCK
Scan Path Management Bit
The Hierarchical
Interface Port (HIP)
opens up a connection
to embedded instruments
when an Assert value
is placed in the U-Cell
after a TAP State- Machine
Update-DR action
The Sel_Instrument Signal
is used to gate the
ShiftEn, CaptureEn,
UpdateEn, and if needed,
the TCK signal of the
target register to enable
the register if selected and
to disable the register if
not selected
The Gateway Register is made of one or more of these SIBs
1687 Hardware Architecture
TRST*
JTAG TAP
Master
Controller
TMS
TAP-IR[n:0]
TCK
THE VIEW FROM THE TAP
In-Line Instruments
This Hierarchy Thread inserts from
WSIo-to-WSOi of the Gateway-A SIB
TDI
Instruments connected to the
Gateway may be connected in
several different schemes:
TDO
1149.1-Zone
1.
A
HIP
WSI
WSO
1
2
3
4
C
D
E
F
2.
3.
B
A Gateway
Interface
Register
5
All Activity in the
1687-Zone is
a DR-Scan from the
TAPs Point-of-View
G
4.
5.
Flat – one gateway-bit is connected to
one instrument
Daisy-Chain – one gateway-bit is
connected to many instrument
serially and simultaneously
Star – one gateway-bit is connected to
some grouping of instruments
Concatenate – one gateway-bit is
connected to a serial string of
instruments that insert into the TDI-TDO
path as they are activated
Hierarchy – one gateway-bit is connected
to an instrument that may support further
hierarchical connections
H
P1687-Gateway
1687-Only-Zone
The 1687 Zone is accessed by opening up Scan Paths to Embedded Instruments
1687 Hardware Architecture
TRST*
TMS
THE VIEW FROM THE TAP
JTAG TAP
Master
Controller
TAP-IR[3:0]
1
1687-Only-Zone
TDI
1
1
2
2
3
3
4
4
1
2
2
WSI
WSO
TCK
3
4
1
2
3
4
5
5
6
7
7
WSI
WSO
1149.1-Zone
WSI
WSO
TDO
8
A
WSI
WSO
B
This Hierarchy Thread inserts itself from the
WSIo to the WSOi of the Gateway-A SIB
C
D
1
1
2
3
4
4
5
5
6
7
8
E
WSI
WSO
F
G
H
This Hierarchy Thread inserts itself from the
WSIo to the WSOi of the Gateway-E SIB
Example of In-Line Instruments opening up
Hierarchical Connections to other Instruments
Gateway SIB Bits may be used within Scan Paths to open new Scan Path Hierarchies
1687 Hardware Interfaces: 1687 Starts at GW
THE VIEW FROM THE CONTROLLER
1
1
2
2
3
3
4
1
4
1
2
2
WSI
WSO
Example of Signals
Required to operate
a 1687 Gateway and
Connected Instruments
3
4
HIP_En
TCK
WSI
WSO
Reset
Capture-En
Shift-En
Update-En
Serial-Out
WSI
WSO
A
B
C
D
E
F
G
H
Gateway is beginning of 1687
1 2 3 4 5
WSI
WSO
Select
WSI
WSO
Serial-In
5 6 7 7 8
This Hierarchy Thread inserts itself from the
WSIo to the WSOi of the Gateway-A SIB
1
1
2
3
4
4
5
5
6
7
8
This Hierarchy Thread inserts itself from the
WSIo to the WSOi of the Gateway-E SIB
Example of use of a non-compliant TAP and
TAP-Controller or other State-Machine
Gateway may be TDR-like or 1500-TAM-like
1687-Only-Zone
The 1687 Standard starts at the Gateway, not the TAP, to allow other future controllers
Basic 1687 Hierarchy Description
Signals defined by Allowed Hierarchical Level and Node Boundaries: Basic Minimalist Structure - The General Case
Level of
Hierarchy
PortList
Root (TAP) Node [Dot-0]
Left
Right
Clock
TCK
to_TCK
Gateway Node (e.g.
Instrument Access Register)
Left
Right
Clock
TCK
to_TCK
Control
Instrument Interface Node
(e.g. Instrument Registered
Wrapper)
Left
Right
Clock
TCK
Control
Control
Leaf Node
(Unwrapped
Raw
Instrument
Signal
Interface)
Left
Clock
Control
TMS
TRSTN
to_ResetN
to_Select
to_CaptureEn
to_ShiftEn
to_UpdateEn
to_SelectLIR
TDI
TDO
Data
to_ScanIn
from_ScanOut
ResetN
Select
CaptureEn
ShiftEn
UpdateEn
SelectLIR
ScanIn
ScanOut
to_ResetN
to_Select
to_CaptureEn
to_ShiftEn
to_UpdateEn
to_SelectLIR
Data
to_ScanIn
from_ScanOut
ResetN
Select
CaptureEn
ShiftEn
UpdateEn
Data
Note: the Instrument
itself is actually
outside of the
Standard since we
do not Specify it in
any way other than
requiring Static
Signals
Data
ScanIn
ScanOut
to_DataBits
from_StatusBits
This portion can be described by a hardware language similar to BSDL with the exception that
hierarchy and dynamic scan chains must be described as well as local or distributed instructions.
DataBits
StatusBits
This portion is beyond BSDL
and this is where the PDL
needs to be applied.
1687 Instrument Interface Bit Definitions
Read-Write Cell
with Self-Check
Read-Only Cell
Serial-In
C/S
Select
HIP_En
WSI
WSO
TCK
Reset
Capture-En
Shift-En
Update-En
Serial-Out
WSI
WSO
A
Sel_WIR
B
C
D
E
HIP
F
G
H
C/S
U
II_0
Status Capture
Combination
Write-Only Cell Self-Checking
Signal Generation II_3
S
U
Read-Write Cell*
Signal Generation II_1
Read-Write Cell
C/S
U
Combination
Status Capture
Signal Generation II_2
II_x = Instrument Interface
C/S
U
Combination
Status Capture
Scan Path Add-In
II_4
* Require Capture to be only
from U-cell output as Self-Check
Cells can be defined similar to Boundary Scan Cells to make up the Interface Register
I’m Confused???
 Why all the complexity? Isn’t Daisy-Chain and Star
enough – it seems to be good enough for the board
world…
 …is there a difference inside the chip as opposed to
outside the chip and on the board?
 And who is supposed to use this stuff anyway?
 How does it help board-test?
I’m Confused???
 Why all the complexity? Isn’t Daisy-Chain and Star enough – it
seems to be good enough for the board world…
• Chip Designers still get measured by successful implementation of
meeting their engineering and budget goals
• Development of the access architecture versus chip tradeoffs is key
 …is there a difference inside the chip as opposed to outside the
chip and on the board?
 And who is supposed to use this stuff anyway?
 How does it help board-test?
I’m Confused???
 Why all the complexity? Isn’t Daisy-Chain and Star enough – it
seems to be good enough for the board world…
 …is there a difference inside the chip as opposed to outside the
chip and on the board?
• Right now, chips have an incredible amount of “embedded” test,
debug, and yield logic that must be accessed
• One key technology is “power management” with requires shutting
down clock domains and even power domains inside the chip
 And who is supposed to use this stuff anyway?
 How does it help board-test?
I’m Confused???

Why all the complexity? Isn’t Daisy-Chain and Star enough – it seems to
be good enough for the board world…

…is there a difference inside the chip as opposed to outside the chip and
on the board?

And who is supposed to use this stuff anyway?

•
Use Case 1: Instruments-Only, Sub-Architectures given to integrator – result is an
“inserted & verified” tradeoff-driven 1687 Architecture
•
Use Case 2: Whole chip with 1687 Architecture given to chip-test engineers for
wafer, package, die-stack test – locating instruments, reusable or auto-generated
vectors; debug & diagnostics; data-collection
•
Use Case 3: Multiple chips with 1687 Architectures given to board-test, systemdevelopment, or for in-system use to assess chip goodness/margins and to help
board-test – locating instruments, reusable or auto-generated vectors; debug &
diagnostics; data-collection; comparison to ATE test results
How does it help board-test?
I’m Confused???

Why all the complexity? Isn’t Daisy-Chain and Star enough – it seems to
be good enough for the board world…

…is there a difference inside the chip as opposed to outside the chip and
on the board?

And who is supposed to use this stuff anyway?

How does it help board-test?
•
Testing complex board is no longer just about interconnect, chip orientation, and
power delivery
•
High-Speed routes and traces must be characterized (e.g. chip-to-chip SerDes
channels with BERT and Eye-Diagrams)
•
Chips must be re-verified in-situ because of different environment conditions from
ATE test
•
This requires operating the test logic and monitors associated with and embedded
within chips
The Connections and Tradeoffs (inside chips)
 4 Non-Hierarchical: Flat, Daisy-Chain, Star, Concatenate
 Hierarchical: Use of the SIB to open nested Gateways
 Tradeoffs:
• Engineering:



Area, Timing, Routing
Power-Thermal
Risk
• Compliance/Efficiency:

IR-Depth, Scan-Path-Depth, Scan-Path-Depth-Stability
• Utility/Automation:




Concurrence
Post-Silicon Flexibility
Protocol-Complexity
Language-Complexity
 The application of tradeoffs results in different architectures
1687 Flat Example
1
FLAT – 1-at-a-Time
Inst.
TDO
Inst.
Inst.
TDI
TAP
TAP-IR
TAP-SM
1. IR maps all Instructions
2. TDI-TDO applied 1-at-a-time
Inst.
CTRL
Inst.
Inst.
Inst.
Inst.
1
Low-Cell Area Impact
High Route-Congestion
High-Scan-Path
High-Control
Wide-IR
Shortest Scan-Paths
Stable Scan-Path
No Concurrency
Simple Protocol
Simple Description
Low Risk
CTRL
Select-Instrument
Reset~
CaptureEn
ShiftEn
UpdateEn
Select-WIR
TCK
1687 Daisy-Chain Example
2
Daisy-Chain
Inst.
Inst.
TDI
TAP
TAP-IR
TAP-SM
1. IR maps all Instructions
2. TDI-TDO to all Instruments
even those that are not active
TDO
Inst.
CTRL
Inst.
Inst.
Inst.
Inst.
Inst.
2
Low-Cell Area Impact
High Route-Congestion
High-Control
Med-Scan-Path
Small-IR
Longest-Stable Scan-Path
Potential Power Problem
All Concurrent
Simple Protocol
Simple Description
High Risk
CTRL
Select-Instrument
Reset~
CaptureEn
ShiftEn
UpdateEn
Select-WIR
TCK
1687 Star Example
3
Star
Inst.
1. IR maps to Instrument groups
2. TDI-TDO organized by groups
Inst.
Inst.
TDI
TAP-IR
TAP
TAP-SM
Inst.
CTRL
Inst.
Inst.
TDO
Inst.
Inst.
3
Medium Cell Area Impact
Med Route-Congestion
Low-Scan-Path
Medium-Control
Med-IR
Med-Stable Scan-Paths
HW-Fixed Concurrency
Simple Protocol
Medium Description
Medium Risk
CTRL
Select-Instrument
Reset~
CaptureEn
ShiftEn
UpdateEn
Select-WIR
TCK
1687 Concatenate Example
4
Concatenate
4
1. IR maps all Instruments
2. TDI-TDO to active selected
instruments only – similar to
daisy-chain but some instruments
are bypassed by wires
Inst.
Inst.
TDI
TAP
TAP-IR
TAP-SM
Inst.
CTRL
Inst.
Inst.
Inst.
TDO
Inst.
Inst.
High-Cell Area Impact
Med Route-Congestion
Low-Scan-Path
High-Control
Wide-IR
Short Scan-Paths
Stable Scan-Path
Concurrency-Scheduling
Post-Si Flexibility
Max- Protocol
Medium Description
Medium Risk
CTRL
Select-Instrument
Reset~
CaptureEn
ShiftEn
UpdateEn
Select-WIR
TCK
1687 Hierarchy Example
5
Hierarchy
1. IR opens Gateway
2. TDI-TDO to SIB only
3. Gateways are distributed
instruction registers
4. Non-Selected instruments are
invisible
TDI
TAP
TAP-IR
TAP-SM
SIB
5
SIB
Inst.
Inst.
SIB
Inst.
Inst.
CTRL
SIB
Inst.
Inst.
TDO
SIB
Inst.
Inst.
Medium-Cell Area Impact
Low Route-Congestion
Low-Scan-Path
Low-Control
Small-IR
Short Scan-Paths
Dynamic Scan-Path
Concurrency-Scheduling
Post-Si Flexibility
Max Protocol
Medium Description
Low Risk
CTRL
Select-Instrument
Reset~
CaptureEn
ShiftEn
UpdateEn
Select-WIR
TCK
Do the Math (we are engineers, after all)
Test
Logic
Reset
1
 Hierarchy –vs- Daisy-Chain:
0
Run
Test
Idle
0
1
TDI
1
Select
Data
Register
SIB[0]
Select
1
An Optimized Access
Architecture
• 5000 Bits of Daisy-Chain takes
Instruct 5000 clocks each
SIB[1] time an instrument
Register
is accessed (flush whole chain, put back whole value with modification
0
0
for 1 instrument)
– 10 accesses
(capture, shift,SIB[2]
updates) requires
Capture
Capture
Instruct clocks (SeDR, CaDR, ShDR, E1DR,
Data
10x5000 shifts
+ 10x5 protocol
1
1
Register
Register
SIB[3]
UpDR) = 50050
clocks 0
0
Shift
Data
Register
0
Shift
Instruct
Register
0
SIB[4]
• With 50 Bits of L-0 SIBs and each Bit expands to 100 Bits of L-1 SIBs
1
1 Hierarchy – addressing
SIB[5]
– is 5000 Bits
in 2-Levels of
the worst case
Exit 1
Exit 1
1
1
Instruct is 50 Shifts + 5 Protocol Clocks to open
instrumentData
(farthest from TDI)
Register
Register
SIB[6]
the 50th L-0
SIB; then shifting 150 Bits to reach
the last instrument in
0
0
0
0
the chain; Pause
times 10 accesses
Pauseresults in 55+10x150=1555 clocks
Data
Register
Instruct
Register
SIB[7]
1 optimal hierarchical
1
• Better more
architecturesSIB[8]
are easily possible –
Exit 2
Exit 2
0
0
Data
instruments
that need to be
accessed a lot should be nearest SIB
Instruct
Register
Register
Bit[1] of the Level-0 Gateway; earlier hierarchySIB[9]
levels should have
1
1
shorter
registers
– the image
Update
Updateshould look like a right-triangle
1
TDO
SIB[10]
Data
Register
Instruct
Register
1
0
0
ScanPath Depth
Tradeoffs vs Connectivity
# of Instruments
Most Non-Hierarchical Flexibility
Most-Instructions (1 per Instrument)
Variable Scan-Paths
Pre-Designed Instrument
GroupsPower – Managed Risk/2
Managed
Some Post-Design Flexibility
Managed Risk
Medium Route/Area Impact
>1000
<500
Most-Flexibility
Most-Instructions
Distributed Instructions
Variable Scan-Paths
Managed Power/Risk
Hidden Instruments
Complex Protocol
Most Support Logic
Most Reusable/Portable
One Instrument at-a-time All Concurrent – Most Power
<100 Available One Instruction – Most Risk
No Concurrence
Mutual-Exclusive Instructions
Minimal Route/Area Impact
No Test Scheduling Flexibility
No Test Scheduling Flexibility
Most Routing
<50 Impact
<10
Flat
Daisy-Chain
Star
Concatenate
Hierarchy
Connectivity
The IEEE 1500 Connection


The 1500 WSP Configuration is ideally made for a Daisy-Chain
connection:
1)
because of the mandatory Bypass Register; and
2)
would be best applied to a TAP Controller that either has no TAP-IR or the TAPIR is concatenated to all 1500 WIRs (so the TAP-SM IR-Side can be used for the
SelectWIR)
3)
more commonly, 2 TAP Instructions select one 1500 WSP
The 1500 Standard has stipulated that Data remain separated from
Instructions:
1)
which is only useful when there is only 1 1500 WSP, or the 1149.1 TAP does not
support its own IR, or when all WIRs and the TAP IR are concatenated when the
State-Machine is on the Instruction-Side
2)
this is why 1500 is still a multiple parallel register architecture with the WIR, BYP,
and any WBR/CDR configured in parallel
3)
the WIR can only be selected by the SelectWIR signal while other registers are
selected/configured by the WIR
The 1500 Connection
CDR
CDR
TDI
WBR
WBR
TDI
BYP
TDO
BYP
TDI
WIR
SWIR
SWIR
CDR
WBR
BSR
BYP
TLR
RTI
SIR
SeDR
SeIR
CaDR
CaIR
ShDR
ShIR
E1DR
E1IR
PaDR
PaIR
E2DR
E2IR
UpDR
UpIR
1500 WSP
1500 WSP
TDR
TDI
WIR
TDO
TDO
TAP-IR
BYP
TDI
WIR
TDO
SWIR
1500 WSP
1149.1 TAP Controller
The use of an 1149.1 Instruction to
select the 1500 units in a daisy-chain
with a 2nd Instruction to select the
WIRs
The SeIR path selects only the TAP-IR
CDR
WBR
BYP
TDI
WIR
TDO
SWIR
1500 WSP
CDR
TDO
TAP Regs Out
WBR
BYP
TDI
1500 Regs Out
WIR
TDO
SWIR
1500 WSP
5 Daisy-Chained 1500 Units with 2 TAP-IR instructions to select 1500 and select WIR
The 1687 Connection
TDI
SIB TDR
BSR
BYP
TDI
SIR
TDI
TDO
WIR | Data | BYP
TDO
TAP-IR
1687 SIP
1149.1 TAP Controller
TDI
In-Line WIRs
WIR | Data | BYP
TDO
1687 SIP
TLR
RTI
SeDR
SeIR
CaDR
CaIR
ShDR
ShIR
E1DR
E1IR
PaDR
PaIR
E2DR
E2IR
UpDR
UpIR
The SeIR path selects only
the TAP-IR
The embedded
instrument interface
registers are selected
by embedded instructions
TDI
TDO
1687 SIP
TDI
TDO
WIR | Data | BYP
WIR | Data | BYP
TDO
1687 SIP
Four 1687 Units with embedded instructions to select Instrument Registers
What HW is missing or not quite described?
 Bandwidth Port
• Internal Instrument Bandwidth
• External Pin/Port Bandwidth
• Parallel versus Serial
 Asynchronous Events
• Instrument Events (triggers, breakpoints, assertions, flags)
• Pin/Port Events (semaphore, sync pulses, interrupts)
• Broadcast Events (resets, starts, stops)
 Instrument-to-Instrument Communication
• Actions of one instrument to another or many
• Actions of multiple instruments aggregated to one instrument
But “Serial and JTAG-Like” Isn’t Enough!!!
 Many have expressed concerned with Bandwidth and non1149.1 Sequences
• More instruments means more data – need higher bandwidth for
some instruments
• Coordination between instruments – need instrument-to-instrument
communication
• Non-1149.1 Operations – need to conduct and describe TAPasynchronous instrument operations such as a “fail flag” or “action
trigger” that occurs when a fail happens, not when the StateMachine happens to be in Capture-DR (e.g. capture the
comparator bus immediately if a fail is detected)
Parallel Operations
 They already occur
•
•
•
•
Only the serial shift-in and serial shift-out are not parallel operations
Capture is a parallel load into the Shift/Capture Cell
Update is a parallel load into the Update Cell
JTAG Operations such as Extest, Intest, Clamp, HighZ are parallel
operations
 To make use of these operations, terminology needs to be
defined
•
•
•
•
•
•
Read: currently capture+scan-out of the Shift/Capture Cell
Write: currently scan-in+update of the Update Cell
TAP Synchronous: Read or Write aligns with State-Machine
TAP Asynchronous: Read or Write not aligned with State-Machine
Data-Operation: Read or Write involving Data
Control-Operation: Read or Write involving WIR
Parallel Notes
 How does this replace a non-JTAG Instrument Interface?
• Loading/Reading/Writing the parallel registers directly turns a
multi-clock-cycle serial operation into a single-clock-cycle
operation – Bandwidth
• Parallel Reads and Writes that are TAP-Synchronous use TCK to
synchronize the data transfers
• Parallel Reads and Writes that are not TAP-Synchronous can use
any clock or trigger to synchronize the data transfers
• Instruments can create the triggers that other instruments would
use to conduct data/control transfers – facilitates Instrument-toInstrument communication
The Example TDR: The Serial Operations
Type-B TDR
A Serial Preload
TDI
Note:
1.
Update Register is Parallel
2.
Both Input and Output side
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
S/C
U
Inst_Data[2]
S/C
U
Inst_Data[3]
SIB
TDO
Sel/Mode
A Serial Read
The Example TDR: A Parallel Load
Some System Bus
Inst_Data /4
Pins/4
Type-B TDR
IDI
TDI
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
S/C
U
Inst_Data[2]
S/C
U
Inst_Data[3]
SIB
TDO
Sel/Mode
IDI
This is a PLoad
= A Capture
IDI
IDI
The Example TDR: A Parallel Read
Some System Bus
Inst_Data /4
Pins/4
Type-B TDR
IDI
TDI
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
S/C
U
Inst_Data[2]
S/C
U
Inst_Data[3]
SIB
TDO
Sel/Mode
IDI
IDI
IDI
This is a PRead
P_Bus /4
Some System Bus
Pins/4
The Example TDR: A Write
Some System Bus
Inst_Data /4
Pins/4
Type-B TDR
IDI
TDI
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
U
Inst_Data[2]
U
Inst_Data[3]
SIB
TDO
Sel/Mode
IDI
This is a P/SWrite
IDI
S/C
= An Update
IDI
S/C
Some System Bus
The Example TDR: A Functional Apply
Some System Bus
Inst_Data /4
Pins/4
Type-B TDR
TDI
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
S/C
U
Inst_Data[2]
S/C
U
Inst_Data[3]
SIB
TDO
Sel/Mode
This is a FCN Apply
Some System Bus
The Example TDR: A Parallel Diagnostic
Some System Bus
Type-B TDR
TDI
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
S/C
U
Inst_Data[2]
S/C
U
Inst_Data[3]
SIB
TDO
Sel/Mode
P_Bus /4
P_Bus /4
Some System Bus
Pins/4
The Example TDR: A Parallel Transfer
Some System Bus
Inst_Data /4
Inst_Data /4
Pins/4
Type-B TDR
TDI
IDI
S/C
U
Inst_Data[0]
S/C
U
Inst_Data[1]
S/C
U
Inst_Data[2]
S/C
U
Inst_Data[3]
SIB
TDO
Sel/Mode
IDI
IDI
IDI
This is a Transfer
P_Bus /4
Some System Bus
P_Bus /4
Connecting Instruments to the Pin Map
Most-likely connection for chips that support 1149.1 Boundary Scan
Functional Data
Borrowed Pin Data
TDO
D
TDI
Q
PIN
D
Capt/Shft
Q
Update
Select Borrowed Pin
CaptureEn
CaptureEn OR ShiftEn
UpdateEn
TCK
Mode=Extest-like
Requires mixed instructions; a GW-CLAMP
in the TAP – a Select_IO in a Local-IR
I’m Board…
 Let’s look at how this impacts the board-level today…
Triple-Point Diagram [PVTF]
Temperature
Cost Limits
ATE Test to
minimum
PVTF points
ATE
Test
Location
Board
Operation
Location
Frequency/Process
Voltage
Must correlate fails found at
Board/System operation to
ATE Test to avoid parametric
NTF (No Trouble Found or
Fail not Repeatable)
Must give Silicon Provider
fail information in context
Silicon Provider must adjust
Mfg Process or must adjust
test to screen closer to
Board/System operation point
In a Disaggregated World: must trace Systematic Si problems
back to ultimate provider – Si Library, EDA Tool, Core Provider,
Chip-Stack, Die-Provider, Design Organization, Mask, Fab, Package…
1687 Hardware Architecture at the Board Level
TCK
TRST*
TMS
TDI
TDO
Chip #1
THE VIEW FROM THE BOARD
TAP-IR[3:0]
1
WSI
WSO
A
B
1
2
3
4
4
5
5
6
7
8
Architecture
Chip-1 GWEN-1 SIB-B
C
TCK
TRST*
TMS
TDI
TDO
At the Board-Level – the two separate chip 1687
Architectures become one seamless unified Architecture
Chip #2
TAP-IR[4:0]
1
WSI
WSO
A
B
C
1
2
3
4
4
5
5
6
7
Architecture
Chip-2 GWEN-3 SIB-B
Example of two 1687 Chips in a Daisy-Chain
Shows Scalability: Note – concern is mixed-use at board of 1149.1 and P1687
8
The Board World Today
Chip 1
TCK
TMS
TDI
TDO
TAP at
Represents
Board
1149.1 (JTAG) is used a Black-Box
Connector
Chip
on board designs to
Design
conduct board test
because it can be used
without external probing
equipment
Chips are delivered
with BSDL Files
to describe JTAG
features
Chip instructions
are not required to
be mapped
identically
Chip 9
Represents
a Black-Box
Chip
Design
Basic Goal of Board Test:
Chip TDI-TDO
connections create
When Chips fail in systems
the access map and
are not required to be
To verifyChipthat
the
correct
chips
and
boards
today,
they
also
identical on all chips
Groupings
or
2
Chip 8
Connections
are in the
correct
the of Star
failspots;
because
environment
Represents
Represents
may impose
a Black-Box
a Black-Box
mutual-exclusivity
orientation
of
chips;
and
And
parametric
margins;
Chip
Chip the
BSDL
Design
Design
Description
completeness ofnot
interconnect;
just interconnect or
Mux 1fails must
orientation; these
a
Inside-the-Chip
BSDL is
be
related
back
to
provider
is generally not
sufficient
b
for
chip JTAG
description
and
connection
Chip 3
Represents
a Black-Box
Chip
Design
known and so is
a Black-Box at
Board Test
Chip 4
Chip JTAG Instructions
Extest, Sample, Preload,
HighZ, etc. allow pins to
be interconnect tested
Represents
a Black-Box
Chip
Design
Hierarchy Lev-0
Scan Path
Linking Module
Chip 5
Let’s look
inside
Represents
a Black-Box
Chip
Design
Chip 6a
Represents
a Black-Box
Chip
Design
Chip 7a
Chips need to be
described in terms
of pins and boundary
scan cells
Daisy-Chained
Chips
Represents
a Black-Box
Chip
Design
Connectivity needs
to be understood
to deliver vectors
to the chips
Chip 6b
Represents
a Black-Box
Chip
Design
Daisy-Chained
Chips
There is a need
Chip 7b
for a simple linear
Represents
indexing system
a Black-Box
to map chips
Chip
Design
Inside-the-Chip Instrument Map
TAP SM
TCK
TMS
TDI
TDO
JTAG Regs
TAP IR
TDO
Instrument Interfaces may
Gateway/Instrument
be viewed as Data Registers
Interface -1.a
orTAP
Instrument
Instruction 1
IR
2
With Registers
3
1a
4
GWENs
5
6
a
Instrument Interfaces may
include
TDI SIBs and can be
classed as Gateways
c/s
Gateway-1
a
b
Instrument
Interface -1.b
Groupings may
be separate IP
Combination
cores
or macros
Instrument-IF
Memory
WSOBIST
Instrument
and
Interface -1.a.a
Gateway WSI
SEL
may
uGroupings
be to align use
1aa
or align latency
Instrument
Interface -1.c.b.a1
1cba1
Scan Compression
Instrument
Interface -1.c.b.a2
Instrument
Daisy-Chained
Bus
Configuration
Instruments
1cba2
Interface -1.c.a
MFG Scan Chains
The Goal: To deliver
Static
1b
Gateway
Drive signals and to extract
BSDL
Gateways group
Static
StatusInstruments
signalsarefrom
Description
1149.1SIBs
1687
Gateway-1.c
and SIBs are
most-likely to be
scan path
a Leaf aInstrument
Node Gateway-1.c.b
Zone dynamic
Zone
delivered “raw”
management bits
a
with signal I/Fs
BSDL is
using ab JTAG-Operated
Gateways enable
insufficient
b
c
Hierarchical Connections
The Handoff
between
the BSDLInterface
Open
Access
for
that allow architectures
Instruments need
to be described in
terms of purpose
and attributes
Logic BIST
Bus Monitor
c
1ca
Instrument
Interface -1.c.b.b
Connectivity needs
to be understood
to deliver vectors
to the instruments
Trace Buffer
1cbb
Zone and the 1687 description
c
d
driven by tradeoffs
There may be fault-tolerant
(HDL)
is the chip identifiier in the
Gateway-2
multi-input connections to Compound
Instrument Individual
BSDL (Entity);MIBan instruction
Gateways may be
Gateway and the
a
minimize broken scan path Gateway
Interface
Leaf
register
it selects
daisy-chained to
There is a need
G1=Default
risk – a multi-scan path
Cell
b
create Hier-Levels
for
an adjustable
G2=Select
Instrument
shared resource
Instrument
indexing
system
Interface
-1.c.b.c
Voltage Monitor
Instrument
c
Core Debug Unit Interface -1.c.d or 2.b.d
to allow mapping
Interface -2.c
Mutual-Exclusive
1cbc
Gateway Gateways can be viewed
1cc
2c
(G1 & G2 cannotasbe
distributed instructions
selected simultaneously)
that represent “bypass” bits
to bypass instruments
Process Monitor
Hierarchy Lev-0
Hierarchy Level-1
Hierarchy Level-2
Hierarchy Level-3
instrument
description
and
hierarchy
Alfred L. Crouch
Chief Technologist & Director of IJTAG R&D
Vice-Chair IEEE P1687 “IJTAG” Working Group
P1687 2008 Update: The Whole Story – Part 2
The IJTAG Features and Capabilities
The Language and Description Portion
BTW – Sept 2008
Crouch
Part II: The Description Languages
 This Section includes the description, documentation,
development and file handoff of the 1687 Architecture
Speaking of IJTAG: Can you see what I am
saying?
 How is all of this Documented and Described?
 What is the “language” (human and otherwise) associated with
1687
 If a chip is full of instruments…and they come from multiple IP
Vendors and EDA tools and the local cube-dwelling design
engineer…and then Bob the Integrator adds this JTAG-like
infrastructure…
 …how does all of this get documented? Where does the
documentation come from? How hard is it to make the
documentation? Who is going to use the documentation? How
do I verify that the documentation is correct?...
Inside-the-Chip Instrument Map
Gateway/Instrument
Interface -1.a
TAP SM
TCK
TMS
TDI
TDO
TAP IR
With
GWENs
JTAG Regs
TAP IR
The Level-0 Gateway
is Selected by a TAP
Instruction and can
be viewed as an
offloaded Distributed
Gateway-1
Instruction Register
a
b
c
BSDL
Description
Gateway
Gateways may be
viewed as Instruction
Registers that hold
instructions that control
and configure other
defined Gateway and
Instrument-Interface
registers
Gateway-2
a
b
c
Mutual-Exclusive
Gateway
(G1 & G2 cannot be
selected simultaneously)
Hierarchy Lev-0
1
2
3
4
5
6
a
1a
The actual Instrument
itself is viewed
as being
Instrument
outsideInterface
of the-1.c.b.a1
HW part
of the 1687 Standard
since it is not being 1cba1
defined or specified
by the Standard
Combination
Instrument-IF
Instrument
and
Gateway Interface -1.a.a
The Name
and the
The Point-of-View: the Scan 1aa
Instrument
Attributes
the
Interfaceof
-1.c.b.a2
Instrument need
Paths and Registers are viewed
Instrument
to be documented as
Instrument
Interface
as-1.bthe Delivery orInterface
CDL
part;
a
part
of the SW part of
-1.c.a
Gateways can produce
the 1687 Standard (e.g.
Leaf Instrument
Node
is viewed signal connections)
1b
“Add_Scan_Path”,
1ca
“Bypass_Other_Register”,
as the IDL part; the
CDL part
“Configure_Other_Register”,
“Modify_Register_Actions”,
may also be viewed
as a data
Instrument Interfaces may
Gateway-1.c
and “Connect_IO_Pins”
viewed as Instrument Instrument
adelivery mechanismtypes
of Instructions
and
a beset
of
Interface -1.c.b.b
Gateway-1.c.b Data Registers since they
a
b
pass only DataBits and
Distributed Instruction-Registers
StatusBits
b
c
dThe Level-n Gateways, by
definition receive their control
MIB- Gateway
and configuration (instructions)
G1=Default
only from other Gateways
G2=Select
Instrument
Interface -2.c
Daisy-Chained
Instruments
1cba2
1cbb
c
Compound
Gateway
Instrument
Interface -1.c.d or 2.b.d
Instrument
Individual
Scan Path
Connectivity
Interface
needs to be documentedLeaf
since it is Instrument
a non-specified Cell
Interface
-1.c.b.c
(variable) part of
the 1687
architecture
1cbc
1cc
2c
Hierarchy Level-1
Hierarchy Level-2
Hierarchy Level-3
IJTAG Language Analysis
Controller Block
1149.1
TAP Link
CellDef Block
SIB
I/O Pin Block
Pin A
Peer Block
Interface
Block
Level-0 GW Level-n GW
Block
Block
W
GW1
GW1stuff is changingR
Warning!
This
S
A
S we speak…meetings are being
as
P
held…skids are being greased…
GW2
GW2
engineers are skulking around in
Interface
dark corners (uh, different ones
Block
than they usually
GWn
GWn hang around)…
W
crayons are being brought to bear
R
…waitresses are being short-tipped
A
for all day meetings in restaurants…
P
Instrument
Block
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Analysis
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
S
S
CellDef Block
SIB
I/O Pin Block
Pin A
GW2
GWn
Level-n GW
Block
GW1
GW2
GWn
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Analysis
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
S
S
CellDef Block
Level-n GW
Block
GW1
Peer Block
Interface
Block
A CellDef Block:
• describes
GW2the cells (BitType)
GW2 similar to
the way 1149.1 defined the BC_2;
Instrument
Block
W
R
A
P
Interface
SIB
Block
• maps available functions to the registers;
GWn
GWn
1) Shift;
W
2) Capture/Load;
R
3) Update/Apply
A
4) Pause/Hold
I/O Pin Block
P
5) Set/Reset
Pin A
6) Open/Close Scan Path
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
Level-n GW
Block
GW1
A Controller Block:
• describes operation sequences & signals;
GW2
• holds Instructions to select & configure
the access architecture;
GWn
• for dot-0 the defined controller is a
compliant 1149.1 TAP Controller;
Pinitems
Blockare needed:
• 4I/O
basic
1)
Entity;
Pin BSDL
A
2) Level-0 Access Instructions;
Pin Register
B
3)
selected;
4) TAP Compliance = True or False
Pin n
GW2
GWn
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
Peer Block
Interface
Block
Instrument
Block
Level-0 GW Level-n GW
Block
Block
W
L
R
E
GW1
GW1
A
A
An I/O Pin Block:
P
F
• Brings chip pins to the Instrument;
GW2
GW2
• is most-likely a shared resource Interface Instrument
Block
(multiple instrument signals will go Block
GWn
GWn
to the same pin);
W
L
R
E
• link from BSDL on 1149.1 chips & HDL;A
A
I/O Pin Block
P
F
• 3 basic items needed:
Pin A
1) the Pin;
Pin B
2) the Instrument Signal(s),
3) the IO Enable Instruction(s)
Pin n
In Terms of Software Code Blocks
1149.1
TAP Link
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
A Gateway/Access Block:
Controller Block
• Holds Architecture Configuration &
Control Instructions that are offloaded
Level-0 GW Level-n GW
from 1149.1
the main controller block;
Block
Block
TAP Link
• basic instruction is toGW1
add/remove GW1
(open/close) scan paths – this
can be viewed as a Bypass action;
GW2
GW2
• other instructions can select,
configure, and organize
the Access GWn
GWn
Architecture resources or Instrument
Interface registers;
PinL-0
Block
•I/O
Note:
Gateway is in BSDL & HDL;
Pin A
• basic items needed:
Pin
1) Bnumber and types of bits;
2) bit functions (instructions);
Pin
IntoTerms
of Software
3) nConnectivity
other GW/IIFs;
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
A Peer Block:
Controller Block
• Holds multiple instrument and
instrument interface rules and
Level-0 GW Level-n GW
information;
1149.1
Block
Block
TAP Link
GW1 and their
GW1
• or multiple Gateways
peer-to-peer connections;
GW2
GW2
• example, 2 daisy- chained elements
have individual bits using a shared
resource, the priority
GWn and encoding
GWncan
be represented here;
• only needed when peer-to-peer
I/O Pin
Block
connections
exist
Pin A
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Peer Block
Controller Block
An Instrument Interface Block: Interface
• Includes
theGW
Wrapper
thatGW
provides Block
Level-0
Level-n
1149.1 the registered static signals to the
Block
Block
W
TAP Linkinstrument;
R
GW1
GW1
A
• receives the raw sticky responses
P
from theGW2
instrument; GW2
Interface
• viewed as a Data Register or an
Block
Instrument
Instruction GWn
Register;
GWn
W
R
• may also include the control or
A
access mechanism selection (serial
I/O Pin Blockor parallel)
P
Pin A
Instrument
Block
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
1149.1
TAP Link
I/O Pin Block
Pin A
Peer Block
An Instrument Block: Interface
• Includes
the Leaf
Block
Level-0
GW Level-n
GWInstrument
declaration and
Block
Blockportion of description
W
needed;
R
GW1
GW1
A
1) Instrument attributes
P
2)
the
signals;
GW2
GW2
3) signal direction;
Interface
4) signal attributes
Block
5) the link to
the Instrument PDL
GWn
GWn
W
R
A
P
Instrument
Block
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
GW2
GWn
I/O Pin Block
Pin A
Pin B
Pin n
A PDL Block:Peer Block
Interface
Instrument
• Includes vector-based
procedures
or
Block
sequences
to configure
and
Level-n GWrequiredBlock
operate
Blockthe instrument;W
L
R
E
GW1
• should be independentA of the access
A
mechanism (associated Pto the raw F
instrument
GW2 signal interface);
Interface Instrument
• PDL can be described
Blockas Methods
Block to
conduct
GWnindividual configurations or
operations (primitives) W
or completeL
R
E
tests (complex);
A
A
F
• Basic PDL is simply: P
1) Reads – Read<Instrument>
2) Writes – Write<Instrument>
3) Applies – Apply <R1, R2, W1…>
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Code Block Rules
Controller Block
Peer Block
1149.1
TAP Link
Level-0 GW
Block
Level-n GW
Block
GW1
GW1
GW2 per
One Controller Block
complete architecture (one
GWn
chip);
Multiple controller structures
may exist within the Block
and their select mechanisms
must be described
GW2
GWn
Level-n GW
Block
GW1
GWn
I/O Pin Block
Pin A
Pin B
Pin n
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Code Block Rules
Controller Block
Peer Block
1149.1
TAP Link
Peer Block
Interface
Level-n GW Block may
An Instrument
only
Block
Block
contain and describe one
GW1
Leaf Instrument Object W
Level-0 GW
Block
GW1
GW2
GW2
An Instrument-Interface
Block
may only contain and describe
GWn
GWn
one Instrument-Interface
Register
Level-n GW
Block
I/O Pin Block
Pin A
Pin B
Pin n
An Instrument Peer Block is
GW1
required when more than one
Instrument+Instrument-Interface
GWn at
group is under a Gateway and
the same hierarchical level (e.g.
a daisy chain of 5 IIFs)
Instrument
Block
L
E
A
F
R
A
P
Interface
Block
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Code Block Rules
Controller Block
A Gateway Block is
a Peer Level-0 GW
1149.1
Block
TAP hold
Link
block in that it may
several Gateway Registers at GW1
the same hierarchical level
and their local connections GW2
Peer Block
GWn
Multiple Gateway Blocks
(Level-0 or beyond) may
exist per hierarchical level – if
more than one block exists,
then peer connections must
I/O Pin Block
be described
Pin A
Pin B
Pin n
Level-n GW
Block
GW1
GW2
GWn
Level-n GW
Block
GW1
GWn
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Code Block Rules
Controller Block
Peer Block
1149.1
TAP Link
Level-0 GW
Block
Level-n GW
Block
GW1
GW1
GW2
Instrument-Interface and
GWn
Gateway connections are
limited to being within the
same level of Parent-Child or
Peer-to-Peer hierarchy;
Only Instrument-Interface to
I/O Pin
Block
Pin-Map
connections can
Pin A
cross hierarchical boundaries
Pin B
Pin n
GW2
GWn
Level-n GW
Block
GW1
GWn
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
Interface
Block
L
E
A
F
Instrument
Block
W
R
A
P
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
Where Does HDL Come From?
 The Chip Provider must supply HDL for end users of the
chip…
 …but as the HDL is being built, its sections come from
several sources – the goal = reusable code sections
IJTAG Language Components
Controller Block
1149.1
TAP Link
I/O Pin Block
Pin A
Peer Block
Interface
Instruments and PDL are
Block or
delivered
by GW
the IP provider
Level-0 GW
Level-n
Block by the EDA
BlockTool that creates
W the
and synthesis-timing
R
GW1 HDL/RTL
GW1
constraints;
A
P
GW2 the standalone
GW2 Instrument
description (IDL) does Interface
not need
to contain any connectivity
Block
GWn information
GWn
W
R
A
P
Instrument
Block
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Gateways, Instrument-Interfaces,
Peer Block
and the connectivity architecture
Interface
are generated by the integrator or Block
Level-0 GW Level-n GW
1149.1 by an insertion tool that evaluates
Block
Block
W
TAP Link tradeoffs and creates an optimal
R
GW1
GW1
architecture;
A
P
GW2
GW2
Interface
Block
GWn
GWn
W
R
A
I/O Pin Block
P
Pin A
Controller Block
Instrument
Block
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
Level-n GW
Block
GW1
the integrator or insertion tool adds
GW2
GW2
to the IDL portion of the HDL by
describing the CDL portion of the
architecture – note
GWnthat the integrator
GWn
may have cores with complete
architectures and may have some
portions of completely described HDL;
I/O Pin Block
Pin A
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Peer Block
Interface Instrument
a valid IJTAG Description
Block may Block
Level-0 GW Level-n GW
just include the Level-0 Gateway
1149.1
Block
Block
W
L
and all subsequent connections
TAP Link
R
E
GW1
GW1
down
to the individual instruments;
A
A
P
F
a complete IJTAG Description
GW2 must GW2
include a description of the controller
Interface Instrument
Block
Block
GWn
GWn
W
L
R
E
A
A
I/O Pin Block
P
F
Pin A
Controller Block
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
The Controller may be generated
GW2
by the integrator or by the tool
used for insertion;
Level-n GW
Block
GW1
GW2
GWn
GWn
or it may be an existing Core or
description generated by an 1149.1
JTAG EDA tool;
I/O Pin Block
the controller
is added to the
Pin A
existing IDL+CDL to complete the
B
HDL Pin
architecture
description
Pin n
Peer Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Components
Controller Block
1149.1
TAP Link
I/O Pin Block
Pin A
Peer Block
The Chip Provider must evaluate
the final HDL to adjust it to meet Interface
Block
the
Proprietary
and End-User
Level-0
GW Level-n
GW
needs
– instruments
that may be
Block
Block
W
used in ATE Testing, but not in
R
GW1
GW1
board-integration or in-system
A
use, must be hidden, obfuscated,
P
or removed
GW2
GW2
Interface
Block
GWn
GWn
W
R
A
P
Instrument
Block
L
E
A
F
Instrument
Block
Pin B
Pin n
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
Code Examples
 What do the code groupings actually look like for these
defined Code Blocks?
 Note: these examples are ASSET’s working language –
not the stuff the 1687 committee is brewing up…
 …the key is to make sure the SAME CONTENT
exists…the syntax can be changed through a parser
IJTAG Language Description
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
GW2
GWn
I/O Pin Block
Pin A
Pin B
Pin n
Parent Block
Interface
Block
Instrument
Block
PDL
Block
Level-n GW
Instrument MBIST {// the Raw Instrument Description Method1
Block
W
L
InstrumentAttributes {
R Functional, Debug,
E Monitor Method2
GW1 IType Test {// Others:
Category BIST {// Others: Monitor, Self-Repair
A
A
Methodn
Class Memory {// Others: Digital, Analog, etc...
SubClass
P SRAM;// Others:
F DRAM, FLASH,
}
GW2
Complexity Simple;// Others: Combin| Seq
}
Interface Instrument
PDL
}
Block
Block
}
Block
GWnSignals {
L
In CLK
{ STypeW
Clock; }
Method1
In ON
{ TAM; R
SafeValue 0; SType
E Control; } Method2
In CACHE_RST { TAM; SafeValue 0; SType Control;
}
A
A
In BIST_RST { TAM; SafeValue 0; SType Control; Methodn
}
In FREEZE { TAM;
P SafeValue 0; SType
F Config; }
Out DONE
{ TAM; SType OpStatus; PIO_Access }
}
Static_Dependencies {// signal dependencies like Oes
In OE { TAM; SafeValue 0; Stype Config; DONE/Z}
}
PDL MBIST; // link PDL file or declared methods here
}
In Terms of Software
Code Blocks
IJTAG Language Description
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
GW2
GWn
I/O Pin Block
Pin A
Parent Block
Interface
Block
Instrument
Block
Level-n GW
Block
Wor Pattern Description
L
PDL MBIST { // the Protocol
Reset {
R
E
GW1Method
apply { "TAM" = 0*; }
A}
A
apply { RESETS = 00;
apply { RESETS = 11;
P}
F
apply { RESETS = 00; }
GW2}
Method Start_MBIST
{
Interface
Instrument
apply { ON = 1; }
Block
Block
}
GWnMethod Get_Status {
L
read { DONE; FAIL;W
}
}
R
E
}
A
A
P
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Description
Parent Block
Interface
Block
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
GW2
GWn
I/O Pin Block
Pin A
PDL
Block
Level-n GW
BlockInterface MBIST_P1687W{ // InstrumentLInterface Method1
{
R
E
Method2
GW1 Signals
In TDI { ScanIn; }
A }
A
Methodn
Out TDO { ScanOut;
iBit bit[35..0]; P
F
Out DONE { PIO_Access; }
GW2 }
Interface Instrument
PDL
InterfaceAttributes {
// OPTIONS:Block
Access Serial {} Block
and/or Access Parallel {}
Block
GWn
Access Serial {
WTrue; // OPTIONS:
L True | False
// TapCompliant
Method1
TapMode Synchronous;
R
E
Method2
}
A
A
}
Methodn
BitOrder {// "MSB" = bit nearest TDI
P
F
iBit bit[0]
{ BitType II_1; Write FREEZE; }
Pin B
Pin n
Instrument
Block
}
iBit
iBit
iBit
iBit
bit[1]
{ BitType II_1; Write ON; }
bit[2..33] { BitType II_0; Read DOUT[31..0]; }
bit[34] { BitType II_0; Read DONE; }
bit[35] { BitType II_2; Write EMODE; Read FAIL; }
In Terms of Software Code Blocks
}
IJTAG Language Description
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
GW2
GWn
Level-n GW
Block
GW1
GW2
GWn
I/O Pin Block
Pin A
Parent Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
From_Output <=> To_Input or List of To_Inputs
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Description
Controller Block
Level-0 GW Level-n GW
1149.1
PIO_Access_Encodings {// dealing with
direct IO pins
Block
Block
Signals {TAP Link
GW1
GW1
Out DONE;
In
In
In
In
In
}
Breakpoint;
Breakpoint_2;
Toggle_Signal;
CLK { Clock; }
TCK { Clock; }
GW2
Parent Block
Interface
Block
GW2
}
Encoding Bkpt_Stop_Enable {
0 => Breakpoint <=> NULL; GWn
GWn
1 => Breakpoint <=> Instrument GL0.GL1.MBIST_1.MBIST.Bkpt_Stop
}
I/O Pin Block
Pin A
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Description
Parent Block
Interface
Block
Controller Block
1149.1
TAP Link
I/O Pin Block
Pin A
Pin B
Pin n
Level-0 GW Level-n GW
Block
Block
W
Gateway "1.c.b_part1"
{ // Gateway Instance R
GW1
GW1
Signals {
A
In TDI { ScanIn; }
P
Out TDO { ScanOut; }
bit[1..0];
GW2 iBit
GW2
In RESET { RESETN; }
In Capture { CaptureEN; }
Interface
In Shift { ShiftEN; }
Block
In Update { UpdateEN; }
GWn
GWn
}
W
BitOrder {
iBit bit[0] {
R
BitType SIB {
A
Interface "1.c.b.a1" = MBIST;
Interface "1.c.b.a2" = MBIST;
P
}
}
}
Instrument
Block
L
E
A
F
Instrument
Block
}
In Terms of Software Code Blocks
L
E
A
F
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
IJTAG Language Description
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
Level-n GW
Block
GW1
GW2
Tap_Connection My_Chip { // My_Chip is Entity Name
Instruction "GWEN1" {
GDR GW1[2..0] = TDR gateway_1[2..0];
GWn
GDR GW1.2.WSIo <=> Gateway
1.TDI;
GDR GW1.2.WSOi <=> Gateway 1.TDO;
}
Instruction "GWEN2" {
GDR GW2[1..0] = TDR gateway_2[1..0];
GW2.1.WSIo
I/OGDR
Pin
Block <=> Gateway 2.TDI;
GDR GW2.1.WSOi <=> Gateway 2.TDO;
} Pin A
}
GW2
GWn
Parent Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
An Alternate View – Instructions
 An alternate view is that there is no specific Hardware Description, but
a map of Instructions – this view requires only the scanpaths to be
described (since they are variable and not fixed by the Standard)
 Different Users may get benefit from different representations:
• Design Verification; ATE Test; Board Test; Yield-Analysis; In-System Test
 There are two basic types of Instructions in the 1687 architecture:
• Those that configure and control the Access Mechanism or Architecture
Configuration (e.g. ScanPaths, Gateways) – Gateway Registers can be
viewed as Distributed Instruction-Registers
• Those that configure and control the Instrument Interface – the InstrumentInterface Register can be viewed as Data-Registers
• Note: the Instrument itself is outside of the Standard since it is not specified or
standardized by the 1687 Standard
IJTAG Language Alternate View
Controller Block
1149.1
The Instruction
TAP LinkView:
Level-0 GW
Block
GW1
Level-n GW
Block
GW1
Parent Block
Interface
Block
Instrument
Block
PDL
Block
Method1
W
L
R
E
Method2
Instruction {
// INSTRUCTION REG | BIT ENCODING | INSTRUCTION NAME [TARGETAREG]
A
Methodn
// ----------------+--------------+-----------------------P
F
GW1.Bits[3:0]{ <= encoding[011X] = Select[GW2] // 2 instructions
enable gateway
reg2
<= encoding[1000]
=
Select_NO_Update[GW2]
//
select
but
block
updates
GW2
GW2
<= encoding[1001] = Select_NO_Capture[GW2] // select but block captures
}
Interface Instrument
PDL
GW2.Bits[1:0]{ <= encoding[00]
= Bypass_IInterface_5[IIF5] // close SIB for IIF_5
Block
Block
<= encoding[01]
= AddPathSelect_IIF_5[IIF5] // open SIB and Select
Block
GWn
GWn
<= encoding[11]
= Clamp[II5] // update, hold data, & close SIB
W
L
Method1
}
GW2.Bits[2]{
<= encoding[0]
= Bypass[GW3] // Close theRSIB for GW3E
Method2
<= encoding[1]
= AddPathSelect[GW3] // Open SIB and Select GW3
A
A
}
Methodn
I/O
Pin Block
}
P
F
The PDL could be as simple as:
Pin A
INSTRUMENT-INTERFACE
| DATA
---------------------+--------------------IIF5
DATA=[01001001001]
Pin<=B
Pin n
In Terms of Software Code Blocks
IJTAG Language Alternate View
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
GW2
GWn
I/O Pin Block
Pin A
Parent Block
Interface
Block
Instrument
Block
Level-n GW
Method1
Block
W
L
The Instruction View – reduces the language to:
R
E
Method2
GW1
The ControllerABlock
A
Methodn
The Instrument Block
P
F
The Instrument-Interface
Block
GW2 The ScanPath/DataPath Connectivity Block
The Instruction Block
The PDL Block
Interface Instrument
PDL
Block
Block
Block
GWn
W
L
Method1
R
E
Method2
A
A
Methodn
P
F
Pin B
Pin n
PDL
Block
In Terms of Software Code Blocks
IJTAG Language Alternate View
Controller Block
1149.1
TAP Link
Level-0 GW
Block
GW1
The Gateway Instructions
Level-n GW
Block
GW1
GW2
• Gateways are Distributed Instruction Registers and
can only do a finite number of things:
GWn
•
•
•
•
•
OpenScanPath-CloseScanPath
Modify a ScanPath (scan path branching/muxing)
Modify another Register’s Actions (e.g. deny Capture)
Configure another Register (e.g. put in Parallel mode)
Connect
a Register
I/O Pin
Blockto IO Pins
Pin A
GW2
GWn
Parent Block
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Interface
Block
Instrument
Block
W
R
A
P
L
E
A
F
Pin B
Pin n
In Terms of Software Code Blocks
PDL
Block
Method1
Method2
Methodn
PDL
Block
Method1
Method2
Methodn
We’re almost there…
 Only a few hundred more slides to go…
Just Kidding!
What’s Left to Define?
 Which Code blocks are optional? Which are required?
• Is a Gateway Level-0 Block required – if there are only a few
instruments, can their Instrument-Interfaces (TDRs) be accessed
directly from TAP Instructions?
 What Keywords are associated with each Code Block?
• Are blocks defined by Keywords such as Instrument, Interface,
Controller, etc.?
 What are the “legal” groupings of Code Blocks? For example:
• More than one Controller Block?
• A Controller Block connected directly to an Instrument Interface with
no Gateway Blocks?
• PDL as a separate file or PDL embedded within the Instrument Block?
• Mixed Gateway and Instrument-Interface Blocks?
 Have we defined all of the HW elements (GDR, IIF, Pins, etc.)?
 Can 1687 concepts be applied above the chip? (Dot-2)
• Board-Level clock/power domains break daisy-chain connections
• Test-Scheduling including multiple chips break star connections
IJTAG Automation Landscape
Core
Acquisition
& Integration
Existing Instruments
Described with 1687
Language file
Concept of Public
Instruments vs Private
Instruments
Concept of
Instrument
Provider
Concept of Delivered
ReUse Vectors
Generation of 1687 Description
Language File and Assessment of
1687 Compliance
Real-Time Generation of 1149.1
JTAG Protocol Vectors to Access
Instruments
Design
Modeling &
Synthesis
Gate-Level
Analysis
Physical
Layout &
Routing
Vector
Generation
& Test
In-System
Operation
EDA Generation of
Instrument Interfaces &
Design
Connectivity to Gateway
Verification
Architectural Exploration of
Instrument Connectivity vs
Structural Tradeoffs
Verification
Verification and Simulation of
Instrument Interfaces and
Gateway Connectivity
Insertion and connection of
Physical Layout Instruments such
as Proc-Mons
Automation of 1149.1 JTAG
Protocol Vector Generation
to Access Instruments
Debug &
Diagnosis
Automated Data Analysis
Processes for Debug,
Diagnosis, and NTF
Perception of Provider – Rollup
#1's
#2's
#1-Ties
Partnering Opportunities
EDA SW
JTAG
HW/SW
ATE HW
In-House SW
Other
1-to-5
1-to-5
1-to-5
1-to-5
1-to-5
IJTAG Insertion & Verification
1.13
2.38
4.71
2.43
2.75
Instrument Modification
2.13
3.43
4.71
1.89
2.00
Instrument Library & Insertion
1.75
3.13
4.57
2.25
1.60
IJTAG Architecture Trade-Off Analysis
1.25
2.29
4.17
3.17
2.20
Instrument Mapping and Cataloguing
2.29
1.63
4.00
2.67
1.75
Vector Reuse and Modification
1.88
2.17
3.29
2.63
2.00
Test Scheduling Analysis
2.71
1.88
3.14
2.43
2.50
Power Characterization
1.86
2.86
3.43
2.29
2.75
Timing Characterization
1.86
3.17
3.13
2.43
2.75
External Interface BIST
2.50
2.14
4.17
2.00
2.25
Internal Interface BIST
2.17
2.17
4.17
2.17
2.25
Debug Translator
3.00
2.00
3.33
2.43
2.40
Scan Compression Diagnostics
1.11
3.00
3.63
3.14
3.25
Scan Dump Analysis
2.00
2.86
3.38
2.57
2.00
MBIST Diagnostics
1.75
3.00
3.86
1.63
3.00
NTF Diagnostics
1.75
2.17
2.71
2.50
2.50
Protocol-Based Test
3.00
1.71
3.17
2.71
2.50
Potential Product Descriptive Name
Roll-Up
Design-Side
Complement
Accesss &
Operation
Data
Collection
& Analysis
Rollup from 20 Industry Thought Leaders
The Identification of Tools and their perceived providers in the marketing survey
Summary-Conclusions
 Several Companies are already implementing IJTAG Concepts
•
•
•
•
They’ve already run into the “volume of instruments” problem
They are beginning to merge DFT, DFD, DFY into Design-for-Access
They are already having “efficiency” and “scheduling” problems
Some companies are struggling with SIP and 1149.1 inadequacies
 The concepts presented have been filtered through real designs and
tradeoff criteria
•
•
•
•
Separation of 1149.1 and P1687
The Gateway; various budget-based connectivity schemes
Instrument Interfaces; parallel data transfers, instrument-coordination
Architecture implementation seems complex but is actually very simple
 The committee work now is focused on Language:
• Describe the architecture (instrument interfaces, Gateways, TAP)
• Describe instrument modes or features
• Generation and Retargeting of vectors
We’re not done yet – keep clicking…
To Finally Answer Ken Parker’s Question…
 How does this chip stuff ever help me and board test…
Inside-the-Chip Instrument Map
TAP SM
TCK
TMS
TDI
TDO
TAP IR
With
GWENs
JTAG Regs
TAP IR
Gateway/Instrument
Interface -1.a
1
2
3
4
5
6
a
1a
Gateway-1
a
b
c
BSDL
Description
Gateway
Instrument
Interface -1.c.b.a1
Combination
Instrument-IF
Instrument
and
Gateway Interface -1.a.a
Instrument
Gateways
Interface
-1.b can
Instrument
produce
Interface
-1.c.a
“Add_Scan_Path”,
“Bypass_Other_Register”,
1b
“Configure_Other_Register”,
“Modify_Register_Actions”,
and “Connect_IO_Pins”
The Instruction View:
types of Instructions
Gateway-1.c
1cba1
1aa
PDL MBIST { // the Protocol Description
Instrument
Method Reset {
Interface -1.c.b.a2
apply { "TAM" = 0*; }
apply { RESETS = 00; }
}
Method Start_MBIST {
apply { ON = 1; }
}
Method Get_Status {
1ca
read { DONE; FAIL; }
}
}
Daisy-Chained
Instruments
1cba2
Instrument
INSTRUCTION REG | BIT ENCODING | INSTRUCTION NAME [TARGET
REG]
Interface -1.c.b.b
Gateway-1.c.b
----------------+--------------+-----------------------a
b
GW1.Bits[3:0]{ <= encoding[011X]
= AddPathSelect[GW2]
<= encoding[1000] = Select_NO_Update[GW2]
b
c
<= encoding[1001]
= Select_NO_Capture[GW2]
1cbb
}
c
d
GW1c.Bits[1:0]{<= encoding[00]
= Bypass_IInterface_5[IIF5]
<= encoding[01]
= AddPathSelect_IIF_5[IIF5]
Compound
Instrument Individual
MIB- Gateway
<= encoding[11]
= Clamp[II5]
Gateway
Interface
Leaf
G1=Default
}
Cell
G2=Select
GW2.Bits[2]{
<= encoding[0]
= Bypass[GW3]
Instrument
Instrument = AddPathSelect[GW3]
<=
encoding[1]
Interface
-1.c.b.c
Instrument
Interface -1.c.d or 2.b.d
}
Interface -2.c
a
Gateway-2
a
b
c
Mutual-Exclusive
Gateway
(G1 & G2 cannot be
selected simultaneously)
Hierarchy Lev-0
1cbc
1cc
2c
Hierarchy Level-1
Hierarchy Level-2
Hierarchy Level-3
Relating TDO Data to Instruments
Scan Out #54: 196 bits
TDO <0100111010001111010101100110010101001001001001…>
Instrument #1
MFG Scan Data
Instrument #2
MBIST Data
What Data is Related?
Core Partition
Scan Structures
Bit Definitions
What Data Mining is Required?
Pattern/Chain/Bit by ATPG Tool
Conversion of Data to Fails
Frequency of Test by STA Tool
#of Toggles/Activity by Power Tool
#3 Instrument #4
LBIST
Bus Data
What Data is Related?
Memory Type
Memory Size
Physical Scramble Table
What Data Mining is Required?
Row/Column by Bit-Mapping Tool
Address/Data by Logic-Decode Tool
Frequency of Test by Timing Tool
#of Toggles by Power Tool
The Board World Tomorrow???
TAP at Board
Connector
TCK
TMS
TDI
TDO
Secret Sauce is the
TAP Synchronization
Chip 1
TAP C.
Represents
a Black-Box
Chip
Design
a
b
1687 Type SIB can
be used as a 1-bit
board bypass
Chip 2
Represents
a Black-Box
Chip
Design
A Chip with Multiple SIBs could
address
chips individually toChip 4
Chip 3
enable only those needed for a
Represents
particular
test or function Represents
a Black-Box
Chip
Design
a Black-Box
Chip
Design
BSDL+HDL
Description
Chips in a Power
Domain can be shut
off completely without
impacting other scan
chain – when on,
scheduling is possible
Chip 9
Represents
a Black-Box
Chip
Design
Chip 6
Chip 8
Represents
a Black-Box
Chip
Design
Daisy-Chained
Chips
Chip 7
Chip 5
Represents
a Black-Box
Chip
Design
Hierarchy Lev-0
Represents
a Black-Box
Chip
Design
Represents
a Black-Box
Chip
Design
Hierarchy Lev-1
Hierarchy Lev-2
Features inside of chips
can be used to test and
characterize board-level
issues
Sample Instruction List
Chip1-Extest<0000>
Chip2-Sample<110
Chip3-Bypass<01101>
Chip2-Clamp<010>
Chip8-Intest<00110101>
Chip4-MBIST: TAP-IR<11100>
GW0[a].IIF1[0..3]<0101>
Chip5-ScanDump:TAP-IR<0011>
GW0[a].IIF5[0..5]<11011>
Chip7-BERT: TAP-IR<1XXX>
GW0[b].IIF1[2]<1>