#### Transcript indDG: A New Model for Double-Gate MOSFET - MOS-AK

indDG: A New Model for Independent Double-Gate MOSFET Santanu Mahapatra Nano-Scale Device Research Lab Indian Institute of Science Bangalore Email: [email protected] Web: http://www.cedt.iisc.ernet.in/nanolab/ Outline • Common versus Independent double gate • Development of indDG Core Single Implicit Equation based IVE Solution Technique for IVE Charge Model • Extension to Tri-Gate • SPICE Implementation • Future Works Common vs Independent DG MOSFET (1) Courtesy: Endo et al. IEEE EDL 2009 Common vs Independent DG MOSFET (2) With IDG MOSFET the design space gets extended from 2D to 3D, which leads to novel circuit design possibilities e.g., Vds Vg1 Vg2 1. High density reduced stack logic, IEEE T-ED 2006 2. Compact sequential circuit, IEEE T-ED 2006 3. Mixer, IEEE T-ED 2005 4. SRAM, IEEE EDL 2009 Dynamic Threshold Voltage Control: Use one gate to drive, other gate to Vth control reshold voltageareand transconductance dynamically that such devices needed to conduct transient and small-signal β 2 I ds = µ [F (Qi 1s , Qi 1d , 2C Gsox ) −1 F2C (Qox (1) i 1d2 , Qi 2d , Gd )] (2) stoin a circuit simulator. As the terminal charge intenovel circuit applications applications as demonstrated L analysis in a circuit simulator. As the terminal charge inte(2) annot be solved directly, different charge linearization literatures [1][4]. An accurate compact model of grals cannot be solved directly, different charge linearization Here whereQi 1 and Qi 2 are the inversion charge densities of the Here Q and Qi 2 are the inversion charge densities of the ues are developed over the years (ﬁrst for bulk [5]rminal charges applicable for all bias conditions for techniques are developed over the years (ﬁrst for bulk ﬁrst [5]-and secondi 1gates given by 2 ﬁrst and second by then for DG [7]-DG [9]conduct MOSFETs) to approximate the Qi 1 2gatesQgiven 2 1 devices arethen needed to and small-signal i2 [6] and for [7][9]transient MOSFETs) to approximate the F (Q , Q , G) = + + (Qi 1 + Qi 2 )+ si t si (3) G i 1 i 2 ition along the channel as a quadratic function of Q = C V − ψ isthein position a circuitalong simulator. As the terminal charge integ1( 2)1 2C 1(ox 2)2 β 2C 2 the channel as a quadratic function i 1( of2) Qi 1(ox2)1(=2) Cox ox V − ψ (3) 1( 2) g1( 2) 1( 2) face potential (or inversion charge densities) so that cannot be solved directly, different charge linearization (2) the surface potential (or inversion charge densities) so and thatG, the coupling factor is expressed as [11] minal charges can be expressed as a compact closed G, the coupling factor is expressed as [11] ques are developed over the years (ﬁrst for bulk [5]the terminal charges can be expressed as a compact closed and 2 Here Q Qi i11 and Q2βi (2ψ 1are the inversion charge densities of the unction of DG source drain surface potentials Qi 2 2 dform then function for [7][9] MOSFETs) to approximate the −V) of and source andend drain end surface potentials Q QBi 2e2β ( ψ 2 − V β) ( ψ2 − V ) i1 G = − B e = − (4) β ( ψ − V ) 1 2 2 = ﬁrst and second gates given by ersion charge densities). In this work we show that G = − B e − B e (4) osition along the channel as a quadratic function of 2 2 (or inversion charge densities). In this work we show that si si si Previous solution (Taur, andsi then Gildenblat) urface potential (or inversion charge densities) so that Q = C (3) workThis is funded by the Indo-French Centre for the Promotion i 1( 2) ox 1( 2) Vg1( 2) − ψ1( 2) work is funded byexpressed the Indo-French Centre forclosed the Promotion rminal charges can beunder asnumber: a compact t 2θy nced Research (IFCPAR) the grant 4300-IT-1. J. Si ONt Si DEVICES of Advanced Research (IFCPAR) under the grant number: 4300-IT-1. J. = V −IEEE ψ (y) 2UTRANSACTIONS sin {ELECTRON h} sinα{ + σ α + σ 2θy (5) T ln of source and drain end surface potentials a,function A. Abraham and S. Mahapatra are with the Nano scale deψ (y) = V − 2U ln h} (5) and G, the coupling factor is expressed as [11] Srivatsava, A. Abraham and S. Mahapatra are with the Nano scale de4LT d θ 4L θ t Si t earch Laboratory, Department of Electronic Systems Engineerd Si version chargeLaboratory, densities). In this of work we show thatEngineervice Research Department Electronic Systems 2 2 merly CEDT), Indian science, C. ing (formerly CEDT),Institute Indian of Institute of Bangalore-560012. science, Bangalore-560012. C. QHere Qi 2oxide i1 β1( ( ψ2)1 − V ) the β ( ψ2 − V ) C are capacitance per unit ox s Anghel with theis Institut Superieur d’Electronique de Paris (ISEP), 21 G 21 =− V2 − Bte sin { h} =(α −2 σθ) − Be (4)area of with the Superieur d’Electronique Paris (ISEP), work is funded by Institut the Indo-French Centre for the dePromotion V g1 Si Assas, 75270, France. emails: {srivatsava, abraham abraham sanﬁrst(second)-gate deﬁned as − ox /t1 σθ is−the si (α siTRANSACTIONS siDEVICES ox 1(cot 2) , { C ON ELECTRON rue deResearch Assas,Paris, 75270, Paris, emails: {srivatsava, san- IEEE + ln 2r h} σθ)silicon = 0 anced (IFCPAR) underFrance. the grant number: 4300-IT-1. J. SDG device has symmetric BC, that leads to dt.iisc.ernet.in, costin.anghel @isep.fr @isep.fr 2UT body capacitance 4L dper unit area deﬁned as si /t si , si , ox tanu}@cedt.iisc.ernet.in, va, A. Abraham and S. costin.anghel Mahapatra are with the Nano scale deVs2 −implied V t Si { h} (α + σθ) additional BCsin(electric field− =0 at y=0), esearch Laboratory, Department of Electronic Systems Engineer+ ln 2r 2 σθ cot (6) { h} QS(α = +− (σ rmerly CEDT), Indian Institute of science, Bangalore-560012. C. Vg2which − V results t SiT sinin { h}very (α + simple σθ)4L d trigonometric 2U IVE + ln − 2r 2 σθcot { h} (α + σθ) = 0 is with the Institut Superieur d’Electronique de Paris (ISEP), 21 where Q 2U 4L T d Assas, 75270, Paris, France. emails: {srivatsava, abraham sancedt.iisc.ernet.in, costin.anghel @isep.fr (5)Qi 1 + Qi Vs2 − V t Si sin { h} (α + σθ) Development of indDG Core Single Implicit Equation Based IVE (1) − 2r 2 σθcot { h} (α + σθ) = available, 0 beenr 2( prop r(7) S+ 1 1( 2) 1) V2( 1) cr = Vg1( 2) − 2UT ln − 4UT + quadra as S− 1 S− 1 S+ 1 closed fo However r 1( 2) r 2( 1) S+ 1 V2( 1) cr = Vg1( 2) − 2UT ln − 4UT + earization S− 1 S− 1 S+ 1 function o 2r 1( 2) (8) change lin S = 1+ r 1( 2) t S i Vs 1 ( 2 ) − V potentials W exp 2L d 2U T bias cond 2r 1( 2) S = 1 +Here r Coxt 1( 2) areV the− Voxide capacitance per (9) unit area 1. When 1( 2) S i s 1( 2) W exp 2L d 2U T ﬁrst(second)-gate deﬁned as ox /t ox 1( 2) , Csi is distributio the silic unit areaperdeﬁned as ofsi /t sithe , chann Here Cbody are the oxideper capacitance unit area si , ox 1( 2) capacitance 2UT A Very Complex Problem Requires Solution of COUPLED implicit equations which has DISCONTINUITY!! + ln 4L d the center of the Si ﬁlm. Vgs1(2) represents the ﬁrst (second) effective gate voltage, i.e., Vgs1(2) = Vgs1(2)applied − Φ1(2) , where Φ1(2) is the work function difference at the respective gates. We ignore the hole concentration, and hence, the PE is valid for ψ > 3/ β. By integrating the PE once using BC1 at the lower bound, we get Single Implicit Equation Based IVE (2) Development of indDG Core dψ dy ψ By indigenous handling of BC, we− (β introduced single implicit equation based IVE V) dψ dψ qni e that is 5x fasterd than coupled = IVE. e(βψ) dψ. dy dy Si dψ − t Si ψ d y |y = − t Si 2 2 COMPUTATIONALLY EFFICIENT GENERALIZED POISSON SOLUTION FOR IDG TRANSISTORS SAHOO et al.: (4) 635 Equation (4) results in dψ = ± dy Aeβψ + G1 (5) where A = 2qni e(− βV ) / β Si , and G1 = { dψ/ dy|y= − t Si / 2 } 2 − Ae(βψ1 ) Now, if we use BC2 instead of BC1 at the lower bound of (4), we get et another form of Velectric Sahoo al., IEEE T-ED, 57, N 3,ﬁeld, 2010which is Fig. 2. Validation of the continuity of the proposed model over the gate voltage variation. Here, the line represents the model, and the symbol represents numerical simulations. To the left side of the Vgs2 = 0.5βψ V line, Vgs1 < Vgs2 , and hence, ψgzp = ψgzp 2 . To the right side of the Vgs2 = 0.5 V line,2Vgs1 > Vgs2 , and hence, ψgzp = ψgzp 1 . Similarly, Vgscr i t is Vgs1cr i t to the left of the dψ = ± dy Ae +G Fig. 4. Ratio of the computational times between the previous model [1] and the proposed model for an asymmetric DG transistor with the following device parameters: t ox 1 = 1.5 nm; t ox 2 = 1.5 nm; t si = 10 nm; ∆ Φ1 = − 0.56 V; and ∆ Φ2 = 0.56 V. The characteristic is almost independent of the values of V . (6) undoped bulkconcept MOSFET as proposed Shangguan [5]. has to use the of the GZP and by critical voltageettoal. select In Fig. 1(a), G is plotted as a function of the interface po1 the exact form from the chosen set as discussed in the next tential ψ for two different values of V . The circles represent 1 gs1 paragraph. Finally, one should solve the corresponding implicit the values of ψ1 obtained or (12) for different Vgs2 ’s equation (11)–(14), i.e., onlyfrom one (11) implicit equation at any given (≤ V ), and they increase with increasing V . To choose the gs1 gs2 bias, for the calculation of the potential proﬁle. As (7) and (8) correct form between (7) and (8), one has to determine whether [and similarly (9) and (10)] were derived on the basis of the sign the correct ψ1 for the given bias lies to the left or the right of G, the GZP plays a major role in determining the ﬁnal form side of ψgzp1 , i.e., whether it lies in the positive or negative of the solution. The GZP is that interface potential at which G1 region. ψ1 shifts toward the negative G1 region [where (8) G becomes zero. Hence, we can have two GZPs, depending holds] when one increases V because the opposing electric on which G we choose in thegs2 ﬁrst step. For example, if one ﬁeld from the second gate increases the possibility of having a chooses (7) or (8) in the ﬁrst step, then one should use the GZP minima of ψ(y) inside the Si ﬁlm. Thus, we introduce a term corresponding G1 denoted ψgzp1 ; otherwise, one should called criticaltovoltage (Vgscrby i t ), which is that Vgs2 at which use ψ . Equating G to zero and solving for to theψinterface gzp2 1( 2) ψ1 obtained from (11) or (12) becomes equal gzp1 . One potential ψ , we get the explicit formulation for the GZP as 1( 2) can derive the expression for the Vgs2cr i t by applying the limit follows: G1 → 0 to (11) and (12) and then replacing ψ1 by ψgzp1 and Fig. 1. (a) GZP and critical voltage at V = 0. (b) Variation of ψgzp 1 and Vgs2cr i t , with quasi-Fermi level V for the same parameters at Vgs21 = 0.4 V. Development of indDG Core G1( 2) → 0, (7)–(10) merge to the following limit values: √ − β ψ1 −2 β A t Si lim ψ(y) = ln e 2 + y+ (17) G 1→ 0 β 2 2 √ − β ψ2 −2 β A t Si lim ψ(y) = ln e 2 + −y+ . (18) G 2→ 0 β 2 2 Solution technique for IVE (1) β V g s1 ( 2 ) Vgs2 by Vgs2cr i t . Similarly, Aε2Si by applying 2 βVgs1cr i t2 can be derived ψ V2gs1( W and e (14) and then2 replacing . ψ (15) the limit →2)0−to (13) gzp1( 2) =G 2 by β 2 Cox1( 2) ψgzp2 and Vgs1 by Vgs1cr i t as follows: Equations (17) and (18) prove the continuity of the model between (7)–(10), respectively. Again, when dψ/ dy → 0, ψ becomes ψ1 as per (7) and (8). Similarly, ψ becomes ψ2 as per (9) and (10) when dψ/ dy → 0, but ψ2 = ψ1 at dψ/ dy = 0. Therefore, the proposed model is also continuous between the G1 and G2 forms. It is worth noting that the previous works [1]–[3] use two different forms (hyperbolic and trigonometric) to model ψ(y). A similar critical voltage concept has been used in the models [1], [3] to choose between the two forms. However, the formulation for critical voltage is implicit in their work, whereas it is explicit in this work. There are some similarities between the solution techniques used in this work Fig. 1. the (a) GZP critical voltage at VHowever, = 0. (b) Variation of ψgzp 1 work and and workandreported in [5]. the previous Vgs2cr , with quasi-Fermi level V for the same parameters at V = 0.4 gs21 i t uses only trigonometric forms and, thus, is not valid underV.all conditions. The same group has also proposed a surface Gbias 1( 2) → 0, (7)–(10) merge to the following limit values: potential equation (not the full Poisson solution) that uses a √ − β ψ1 single implicit− equation [6]. Asβin A their other 2 t Si work, it is also 2 + lim ψ(y) = ln e forms y +valid under all(17) based and2 is not bias G 1 → 0 on trigonometric β 2 conditions. √ − β ψ2 −2 β A t Si lim ψ(y) = ln e 2 + −y + . (18) G 2→ 0 β 2 2 III. R ESULTS AND D ISCUSSIONS Here, W represents the √ Lambert function. Interestingly, ψ gzp 1( 2) −2 β equal At Sito the− βsurface ψV potential of an gzp1( 2) is approximately 2 ln + e gs2( 1) cr i t = β 2 undoped bulk MOSFET as proposed by Shangguan et al. [5]. In Fig. 1(a), G1 is plotted as a function of the interface po√ . The circles represent tential ψ1 for two different values of Vgs1 εor A for different V ’s Si (12) the values of ψ1 obtained − from (11) . gs2(16) √ − β ψ gzp 1( 2) β A t Si (≤ Vgs1 ), and they increase with increasing V . To choose the gs2 2 Cox2( 1) + e 2 correct form between (7) and (8), one has to determine whether the correct ψ1 for the given bias lies to the left or the right Therefore, for V 1) > Vgs2( 1) cr i t , one has to choose the side of ψgzp1 , i.e., gs2( whether it lies in the positive or negative G1( 2) < 0 form, i.e., (8) or (10), otherwise, one has to choose Gbetween region. ψ shifts toward the negative G region [where (8) 1 (7)1and (9). In Fig. 1(b), we have1 shown the variation holds] when one increases Vgs2 because opposinglevel electric of ψgzp and Vgscr i t as a function of the the quasi-Fermi (V ), ﬁeld from the second gate increases the possibility of having a and both of these quantities are found to be saturated at a high minima of ψ(y) inside thesquare Si ﬁlm. Thus, V as they depend on the root of A.we introduce a term called critical voltage (V ), which that Vgs2 of at the which gscr it and (18)validated prove the of the model Now, coming to the question of theiscontinuity pro- Equations In Figs.(17) 2 and 3, we our continuity model against a numerical ψposed from (11) or (12) becomes equal to ψ 1 obtained gzp1 model between various forms, we notice that. One when between simulation for V respectively. = 0. The numerical solution (7)–(10), Again, when dψ/ of dy the → 0,PEψis can derive the expression for the Vgs2cr it by applying the limit becomes ψ as per (7) and (8). Similarly, ψ becomes ψ as 1 2 G1 → 0 to (11) and (12) and then replacing ψ1 by ψgzp1 and peron(9) and04,2010 (10) when dψ/EST dy → butXplore. ψ2 = Restrictions ψ1 at dψ/apply. dy = 0. Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. Downloaded March at 21:12:31 from0, IEEE Vgs2 by Vgs2cr it . Similarly, Vgs1cr it can be derived by applying Therefore, the proposed model is also continuous between the the limit G2 → 0 to (13) and (14) and then replacing ψ2 by G and G forms. It is worth noting that the previous works 1 2 ψgzp2 and Vgs1 by Vgs1cr it as follows: [1]–[3] use two different forms (hyperbolic and trigonometric) Singularity @ γ = π for Trig IVE Vgs2( 1) cr it = Discontinuity @ G = 0 for √ both Trig −2 β At and Hyp IVE β ln Si 2 + e − β ψ g zp 1 ( 2 ) 2 Conventional NR method doesn’t GUARANTEE convergence!! to model ψ(y). A similar critical voltage concept has been used in the models [1], [3] to choose between the two forms. However, the formulation for critical voltage is implicit in their work, whereas it is explicit in this work. There are some Development of indDG Core Solution technique for IVE (1) • We use RBM (Root Bracketing Method) instead of NR-based method to achieve guaranteed convergence. • We did a rigorous study of all RBMs available in the literatures (~20). And finally choose LZ4 technique (D. Le, ACM T-MS 1985) to solve the IVEs. But RBM requires solution space…. So we need to solve ONE more implicit equation, to find the solution space for Trig/Hyp IVE. We do some smart optimization of solution space to improve overall computational efficiency. And so we need to solve THREE implicit equations SEQUENCIALLY (one to choose mode, one to find solution space and finally the main IVE) to calculate the surface potential. Srivatsava et al., IEEE T-ED, V 58, N 6, 2011 Abraham et al., IEEE T-ED, April, 2012 Development of indDG Core THREE MODES OF OPERATION The Charge Model : Issues with existing Model T T HH TH Line: Model (G. Dessai, IEEE T-ED 2010) Symbol : Numerical Development of indDG Core The Charge Model: Charge linearization Concept As the exact solution of the integrals are not available ‘charge linearization’ techniques are introduced over the years to approximate F as quadratic function of surface potentials (or charge densities) so that closed form expressions for terminal charges are obtained. Development of indDG Core The Charge Model : The NLF Factor To approximate F as quadratic function of ψ1 or ψ2 (Qi1 or Qi2 ), they should hold linear-relationship along the channel for a given bias condition. Development of indDG Core The Charge Model: Piecewise Linearization Technique We segment the channel, so that for each segment ψ1 holds linear relationship with ψ2 so that conventional charge linearization technique could be applied to formulate the Terminal Charges. Srivatsava et al., Appearing in IEEE T-ED, 2012 Development of indDG Core The Charge Model: Comparison of linearization • indDG charge model is based on the relationship of the surface potentials • It is derivative free and thus numerically robust SDG with small Tox asymmetry (indDG-c) • There will always be some amount of asymmetry between the gate oxide thicknesses due to process variation and uncertainties • indDG-c handles the asymmetry as it is based on the relationship between surface potential (which is linear for this case) • We use an accurate analytical approximation of surface potential by novel perturbation technique Simple closed form function of Bias and device parameters, derived from the IDG IVEs Srivatsava et al., IEEE T-ED, April, 2012 Including Body Doping Tox1=1nm Tox2=1.5nm Tsi = 10nm Tox1=Tox2=1nm; Tsi = 20nm Tri Gate Extension • Tri Gate MOSFET cannot be model like Bulk or DG as the 3D Poisson Equation cannot be approximated as 1D Poisson for long channel cases. • Models for Tri Gate are developed on top of the planner DG Models Model Implementation Model is implemented in Silvaco SmartSpice through Verilog-A interface S/D Symmetry of Terminal Charge 101 Stage Ring Oscillator Also successfully simulated 8-bit Ripple carry adder, Jhonson Counter Future Plans To include Small geometry effects, NQS, Noise, extrinsic elements to make it applicable for practical devices… Acknowledgement My Masters and Ph.D. students Department of Science and Technology (DST), Government of India Dr. Ivan Pesic and his team @ Silvaco International