20140923_twepp_soi_miyoshi_v3 - Indico

Transcript 20140923_twepp_soi_miyoshi_v3 - Indico

1/25 Front End Electronics for SOI Monolithic Pixel Sensor T. Miyoshi, Y. Arai, Y. Fujita, K. Hara 1 , S. Honda 1 , Y. Ikegami, Y. Ikemoto, I. Kurachi, S. Mitsui, A. Takeda 2 , K. Tauchi, T. Tsuboyama, M. Yamada High Energy Accelerator Research Organization (KEK) 1 Univ. of Tsukuba 2 Kyoto University v.3

23/9/2014 (Tuesday) 11:35 - 12:00 ASICs 1

2/25 Introduction Progress of SOI sensors Sensor layout Pixel layout and circuit Current issues and solutions Future plan and summary Outlines

MPW FY13-1

3/25 SOI Wafer for monolithic sensor Smart cut TM by Soitec Oxidation Implantation Cleaning and bonding Splitting circuit Initial silicon sensor High Resistivity Silicon: Two choices N-type Czochralski, NCZ, 700 Ohm-cm, 300 m m-thick N-type Float Zone, NFZ, 2-7k Ohm-cm, 500 m m-thick Low R High R SOI wafer 3

4/25 Insulator (SiO 2 ) SOI Monolithic pixel sensor

Low R Si High R Si

Targets High-Energy Physics X-ray astronomy Material science Non-Destructive inspection Medical application The features of SOI monolithic pixel sensor • • • • No mechanical bump bonding. Fabricated with semiconductor process only Fully depleted (thick & thin) sensing region with low sense node capacitance (~10 fF@17 m m pixel)  high sensor gain • ・ SOI-CMOS; Analog and digital circuit can be closer  Wide temperature range (1-570K) smaller pixel size Low single event cross section Technology based on industry standards; cost benefit 4

5/25 Process Summary 25mm x 30mm • • • KEK organizes MPW runs twice a year Mask is shared to reduce cost of a design Including pixel detector chip and SOI-CMOS circuit chip Process 0.2

m m Low-Leakage Fully-Depleted (FD) SOI CMOS (Lapis 1 Poly, 5 Metal layers (MIM Capacitor and DMOS option) Semiconductor Co. Core (I/O) voltage : 1.8 (3.3) V Ltd.) SOI wafer (200 mm f =8 inch) Top Si : Cz, ~18  -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer thickness: 725 m m  thinned up to 300 m m (Lapis) or ~50 m m (commercial process) Handle wafer type: NCZ, NFZ, PFZ, double SOI Backside process (2011~) Mechanical Grind  Chemical Etching  Back side Implant  Laser Annealing  Al plating 5

6/25 (12 m m pixel) Progress of SOI monolithic sensors beans Integration-type pixel sensors (8 m m pixel) Test chart X-ray tube Target:Cr

m slit

screw X-ray phase-contrast image (INTPIX5) 16 keV monochromatic CERN beam test in 2011 CERN SPS NORTH H4-H6 p+ 55%, p 39%, K 5% 50 m m-thick CZ INTPIX3e X-ray image (FPIX) XRPIX3 30 m m pixel Kyoto Univ.

S/N ~ 15

4 layers of INTPIX3e (16 m m pixel) Univ. of Tsukuba Energy loss 6

7/25 An example of Sensor layout (1) INTPIX7 (MPW FY13-1) Integration-type pixel sensor Bias ring (n+) 18mm HV ring (p+)

Pixel area (12

m pixel) 1408 x 1408

Pixel area

275-490 m m

N(0V) P(+HV)

P Enge of the chip (side view) SiO2(yellow) 7

8/25 An example of Sensor layout (2) 18mm INTPIX7 (MPW FY13-1) Pixel array Raw Address (RA) decoder Column Address (CA) decoder Column buffer, analog buffer, Bias circuit

Decorder (RA) Pixel array Bias circuit Column Buffer Decorder (CA)

Pixel area (12

m pixel) 1408 x 1408

IO pad array

IO pad array 8

9/25 Pixel layout and circuit (1) INTPIX7 Pixel size 12 m m CDS circuit in pixel Sense node Sense node 1 + Transistor 9 + MIM capacitor 1 in 12 m m 2 12m

10/25 Pixel layout and circuit (2) FPIX Pixel size 8 m m No STORE, no storage capacitor VDD COL_OUT READ_X Sense node 8 m m

-V +V

VRST GND Sense node 1+Transistor 6 In 8 m m 2

Min. distance between sense node and transistor ~ 1

11/25 Current issues and solutions another SOI layer Buried P-Well (BPW) SiO 2 Si

1. BPW process

: effective to analog circuit in a pixel

2. Double SOI wafer

: effective to digital circuit in a pixel 11

12/25

Back-gate effect

13/25 Dope density [/cm 3 ] Geometry of TCAD simulation for BPW effectiveness study W source nmos [m m] Lg = 0.3

Wg = 5 drain 1.1

m m Tsoi=40nm 1 m m p1 5 m m p+(1e20) 15m m

Buried P-Well(BPW) (1e12-1e17)

BOX p2 p+(1e20) n- bulk (6e12) backbias 0-500V HyENEXSS (TAC, Japan) 13

14/25 Simulation result for BPW effectiveness study

Back gate effect with p dose

0,5 0,4 0,3 0,2 0,1 -0,1 -0,2 0 0 100 200 300

Back bias (V)

400 500 600 Dope density [/cm 3 ] 1.00E+17 9.00E+16 8.00E+16 7.00E+16 6.00E+16 5.00E+16 4.00E+16 3.00E+16 2.00E+16 1.00E+16 1.00E+12 “Vth>0.4V” @ back bias > 100 V  p dose > 5e16

Increase of maximum voltage in which tr. works

15/25 Transition analysis Crosstalk study (TCAD Simulation) Single SOI w/o BPW Pulse 1V NMOS source

Blue: Vsource Black: Ip1 Red: Ip2

0.1

m A 1ns Single SOI w. BPW Sense1,2 Pulse 1V NMOS source 0.1

m A Sense1 Sense2 1ns

Crosstalk increase by BPW

16/25 An example of crosstalk observation (XRPIX2/2b,3/3b) TIPP2014 A. Takeda (Kyoto Univ.) For X-ray astronomy Event-driven R/O circuit

Comparator in pixel

30 m m pixel Anti-coincidence (NXB rej.) Hit-pattern (NXB rej.) Direct pixel access (X-ray RO) 16

17/25 A. Takeda,PIXEL2014 An example of crosstalk XRPIX2/2b (Kyoto Univ.)

A large spike

Due to Wiring of an analog and a trigger signal lines

Sensor-circuit crosstalk?

(100mV/div)

18/25 Double SOI pixel sensor STEM image SOI wafer Initial silicon * Substrate: NCZ or PCZ wafer Additional shield layer Shield the back gate effect Compensate effect of box charge Shield the sensor to circuit crosstalk 18

19/25 Geometry of TCAD simulation For double SOI effectiveness study Dope density [/cm 3 ] W 0V p1 5 m m 5 m m p+(1e20) 15m m source nmos [m m] Lg = 0.3

Wg = 5 drain 1.1

m m Tsoi=40nm box SOI2 5 m m 1 m m p2 p+(1e20) n- bulk (6e12)

20/25 Transition analysis Crosstalk (TCAD Simulation) Single SOI Pulse 1V at NMOS source

Blue: Vsource Black: Ip1 Red: Ip2

0.1

m A Sense1,2 1ns Pulse 1V at NMOS source Double SOI 0.1

m A Sense1 Sense2

Crosstalk can be suppressed in double SOI sensor

21/25 Development of double SOI pixel sensors 2012 The first prototype  breakdown study 2013 The second prototype  pixel sensor, rad. hard study (TIPP2014, VERTEX2014, IEEE-NSS 2014) 2014 The third prototype  Still under fabrication!  chips will be delivered in October 21

22/25 Shaper output of beta-ray signal (PIXOR) Double SOI (d-SOI) : The second prototype Tohoku Univ.

“Superpixel” includes pre-amp., shaper, discri.

readout circuit Y x Y. Ono et al., NIMA 731 (2013) 266-269 N. Shinoda, Master thesis, March, 2013 Sr-90 beta-ray beta-ray signals were observed successfully from Pre-amp.&shaper cir. with d-SOI Discriminator output is not confirmed yet.

23/25 Future plan; Counting-type pixel (double SOI) Under development Test di sfto sclko Preamp.

VTH P-type sensor (p- bulk) -Vdet Discri.

15bit counter Test on/off Fine vth (3bit) do sfti sclki rst Ci[0:3] Control register Co[0:3] 23

24/25 Future plan; Counting-type pixel (double SOI) Under development

15bit counter

SOI2 contact 50 m m Sense node

Preamp.

Discri.

Control register

25/25 Summary Several SOI pixel sensors have successfully been fabricated 3 issues; the back-gate effect, radiation hardness, sensor-circuit crosstalk 1. The back-gate effect Integration-type pixel sensors works thanks to BPW process 2. Sensor-circuit crosstalk can be suppressed by applying double SOI 3. Radiation hardness (is not mentioned in this talk) SPRiT (SOI Portable Radiation imaging Terminal) Double SOI pixel sensors: The 1 st trial 2012 The 2 nd trial 2013 The 3 rd trial 2014 Chips will be delivered in October.

optimize pixel design with p-type DSOI sensors http://rd.kek.jp/project/soi/ 25

Supplement 26

Various Implantation Options in Sensor part CPIX14 Y.Arai

SOI process

Requirements to the Pixel Detectors

Hadron colliders:

• • • High total integrated dose and neutron flux LHC ATLAS inner Pixel detector: ~160 kGy and 10 15

eq /cm 2 (x10 for HL-LHC) Immunity to Single Event Effects Very high event pile-up

Linear colliders:

• High granularity • Complex readout scheme 140 120 100 80 60 40 20 0 0

ATLAS

Online 2012, s =8 TeV 5 10 15 20 25 30 ò Ldt=21.7 fb -1 35 < m > = 20.7

40 45 50 Mean Number of Interactions per Crossing  SOI pixel detector fulfill these requirements.

M. Yamada, PIXEL2014 2014/09/01 ATLAS Luminosity Public Results: https://twiki.cern.ch/twiki/bin/view/AtlasPublic/L uminosityPublicResults PIXEL2014 28

M. Yamada, PIXEL2014

Cancelling the TID effects

Compensation of TID effect

Threshold of transistor shifts negatively due to positive potential from BOX .

 Applied negative potential to SOI2 (VSOI2).

Test samples (NMOS and PMOS)

• several

and

of Tr • low, normal and high threshold V • Three kinds of body connections Several types of transistors are used for readout circuit.

We evaluated the radiation damage of transistors processed on double SOI.

(BF) (S-TIE/S-TIE2) (MULTIB-TIE) Irradiation: 60 Co

𝛾

-ray from 3 kGy up to 2 MGy

at Takasaki Advanced Radiation Research Institute, JAEA ( http://www.taka.jaea.go.jp/index_e.html

) 2014/09/01 PIXEL2014 29

M. Yamada, PIXEL2014

-

after Irradiation with VSOI2

D -

G curves with VSOI2 to cancel positive potential from BOX after irradiation of

200 kGy

NMOS Body-tie PMOS Body-tie

th Recover

● VSOI2=0V ● VSOI2=-1V ● VSOI2=-3V ● VSOI2=-2V ● VSOI2=-4V ● VSOI2=-5V ● VSOI2= 10V ● VSOI2=-15V We observed recovery of

D -

G 2014/09/01 curve after irradiation with VSOI2.

PIXEL2014 30

M. Yamada, PIXEL2014

Double SOI

Pre-irrad

Response to infrared laser of 1064 nm wavelength and 10 ns pulse duration.

VSOI2=0V VSOI2=-10V

The average ADC count as function of the square root of the bias voltage for sensor.

 Obtained similar linearity and sensitivity to pre-irradiation with VSOI2=-10 V .

S. Honda et al., TIPP12014, 2-6 June 2014, Amsterdam 2014/09/01 PIXEL2014 The pixel images after 100 kGy could not obtain but recovered with VSOI2=-10V.

6000 5000 preirrad 100kGy VSOI2=-10V 4000 3000 2000 1000 0 0 2 4 6 8 V_RST(preirrad)=550mV V_RST(100kGy)=950mV INT_TIME=120ns 10 12 14 16 18 20 Sensor Bias ( V ) 31

K. Hara, VERTEX2014 TID: Target Radiation Levels SOI is immunity from SEEs for smaller active area, enclosed in oxide layers ideal for space applications 50nm 200nm ~100um TID: Total Ionization Damage is rather complicated …

Wide dose range of applications:

LHC pixel ~ 500 kGy, 10 15 n eq /cm 2 @ATLAS (

10 for HL-LHC) Belle-II ~ 10 kGy/y, 2x10 12 n eq /cm 2 /y ILC (e.g., ILD @

=15 mm) ~ 1 kGy/y, ~10 11 n eq /cm 2 X-ray imaging: kGy/y ～ MGy/y /y …

Radiation damage studies done so far:

proton irradiation to 10 16 n eq /cm 2 60 Co γ irradiation to 5 MGy for DOUBLE-SOI : 60 Co γ irradiation to 2MGy K. Hara, VERTEX2014, Macha Lake, Czech Sep.16-19 32

M. Yamada, PIXEL2014

PIXOR

Digital part

It manages holding of binary data from discriminator and timing comparison of hit and trigger.

Generally a trigger decision takes several micro seconds from the actual event time in high energy experiment (trigger latency).

Evaluated the overall circuit of digital part with a test-pulse.

Clock Trigger latency Trigger latency Digital circuit could store the hit information of the signal during the trigger latency and sent a binary hit information as expected.

2014/09/01 PIXEL2014 Y. Ono et al., NIMA 731 (2013) 266-269 N. Shinoda, Master thesis, March, 2013 33

M. Yamada, PIXEL2014

PIXOR

Vertex Detector of Belle II

Two layers of pixel detector

DEPFET

Four layers of silicon strip detector

SVD SVD DEPFET We are aiming PIXOR is installed as 1st layer of SVD for Belle II upgrade.

M.Friedl et al., “The Silicon Vertex Detector of Belle II”, VERTEX2011, 19-24 June 2011, Rust, Lake Neusiedel, Austria 2014/09/01 PIXEL2014 34