Transcript Chapter 4 -- Modular Combinational Logic

Chapter 4 -- Modular Combinational Logic
Decoders
y0
LSB
x0
y1
x1
n-to-2n
Decoder
MSB xn-1
y2n-1
Decoder Realization
LSB A
LSB A
m0
MSB B
m0
MSB B
m1
m1
m2
m2
m3
m3
(a)
(b)
m1
LSB A
m0
MSB B
m2
(c)
m3
C
B
A
More complex decoders
A
B
m0 = CBA
m1 = CBA
A
C
A
B
m2 = CBA
A
m3 = CBA
A
B
m4 = CBA
A
C
m5 = CBA
m6 = CBA
A
B
A
m7 = CBA
m0
m1
m2
m3
m4
m5
m6
m7
(b)
(a)
k0
C
m0
m1
m2
m3
m4
m5
m6
m7
m8
m9
m10
m11
m12
m13
m14
m15
k1
2-to-4
D
MSB
k2
k3
l1
l2
l0
l3
2-to-4
B
(c)
A
LSB
Example 4.1 -- Realize f(Q,X,P) =
m(0,1,4,6,7) = M(2,3,5)
0
P
X
Q
A
1
B
2
C
3
0
P
X
f(Q, X, P)
Q
A
1
B
2
C
3
4
4
5
5
6
6
7
7
(a)
f(Q, X, P)
(b)
Example 4.1 (concluded)
0
P
X
Q
A
1
B
2
C
3
0
P
X
f(Q, X, P)
Q
A
1
B
2
C
3
4
4
5
5
6
6
7
7
(c)
f(Q, X, P)
(d)
K-Channel multiplexing/demultiplexing
Multiplexer
Demultiplexer
Ain
Aout
Bin
Bout
SW1
Kin
SW2
Kout
Single
channel
(a)
Ain
Single
channel
a
Aout
a
Bin
Bout
b
É
b
Kin
É
Kout
k
k
(b)
Figure 4.22
Four-to-one multiplexer design
D0
D1
4-to-1
Multiplexer
D2
Y
D3
B
A
Selection code
(a)
B
A
Y
0
0
1
1
0
1
0
1
D0
D1
D2
D3
(b)
D0
D0
D1
D1
Y
Y
D2
D2
D3
D3
0 1 2 3
2-to-4
Decoder
B
A
(c)
B
A
(d)
Use a 74151A multiplexer to Realize
f(x1,x2,x3) = m(0,2,3,5)
VCC
74151A
i
0
1
2
3
4
5
6
7
C B A
x1 x2 x3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y
f
1 D0 = 1
0 D1 = 0
1 D2 = 1
1 D3 = 1
0 D4 = 0
1 D5 = 1
0 D6 = 0
0 D7 = 0
(a)
D0
D1
D2
D3
D4
Y
D5
W
D6
D7
G
C B A
x1 x2 x3
Selection code
(b)
Figure 4.30
f(x1, x2, x3)
Half Adders
xi
xi
yi
HA
xi
yi
ci
si
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
si
yi
ci
(b)
ci
si
(c)
(a)
Figure 4.35 (a) -- (c)
Full Adders
xi
xi
yi ci-1
FA
ci
xi
yi
ci-1
ci
si
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
si
yi
si
ci-1
(e)
ci
(d)
(f)
xi
yi
si
ci-1
(g)
Figure 4.35 (d) -- (g)
Ripple Carry Adder
xn-1 yn-1
cn-2
c1
x1 y1 c 0
FA
FA
x0
y0
HA
cn-1
zn
(end carry)
zn-1
z1
Figure 4.36
z0
Addition Time for a Basic Ripple-Carry Adder
Let tgate = the propogation delay through a typical logic gate
Half adder propagation delays
tadd = 3 tgate
tcarry = 2 tgate
Full adder propagation delays
tadd = 3 tgate
tcarry = 2 tgate
Ripple-Carry Adder (n-bits)
tadd = (n - 1)2 tgate + 3 tgate
= (2n + 1) tgate
SN7482 Two-Bit Pseudo Parallel Adder Module
A2
B2
S2
GND
C2
NC
NC
14
13
12
11
10
9
8
B2
A2
S2
C2
S1
A1
B1
C0
1
2
3
4
5
6
7
S1
A1
B1
VCC
C0
NC
NC
(a)
Package Pin Configuration
SN7482 Pseudo Parallel Adder -- Truth Table
Inputs
Outputs
When C0 = L
When C0 = H
A2 A1
B2 B1
C2 S2
S1
C2 S2
S1
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
L
H
L
L
H
H
L
H
H
H
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L
L
L
L
H
L
L
H
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
(b)
L
L
H
H
L
H
H
L
H
H
L
L
H
L
L
H
L
H
H
L
H
H
L
L
H
L
L
H
L
L
H
H
SN7482 Pseudo Parallel Adder -- Logic Diagram
C0
A1
S1
B1
C1
S2
B2
A2
C2
(c)
SN7482 Two-Bit Adder -- Logic Equations
C1 = C0A1 + C0B1 + A1B1
(4.20)
1 = C0C1 + A1C1 + B1C1 + A1B1C0
= C1(C0 + A1 + B1) + A1B1C0
= (C0+A1)(C0+B1)(A1+B1) (C0 +A1+B1) +A1B1C0
= (C0+ A1B1)(A1+B1)(C0 +A1+B1) +A1B1C0
= [C0(A1+B1)+ C0A1B1](A1+B1)+A1B1C0
= C0A1B1+C0A1B1+C0A1B1+A1B1C0
= C0  A1  B1
(4.21)
Similarly
C2 = C1A2 + C1B2 + A2B2
2 = C1  A2  B2
(4.22)
Add Time for SN7482 Adder Circuits
SN7482 propagation delays
t1
tC1
t2
tC2
= 5 tgate
= 2 tgate
= 6 tgate
= 4 tgate
SN7482-based ripple-carry adder (n-bits)
tadd = (2n + 2) tgate
SN7483 Four-Bit Adder Module
B4
S4
C4
C0
GND
B1
A1
S1
16
15
14
13
12
11
10
9
S4
C4
C0
B1
A1
B4
S1
A4
A2
S3
A3
B3
1
2
3
4
A4
S3
A3
B3
S2
B2
5
6
7
8
VCC
S2
B2
A2
(a)
Package Pin Configuration
SN7483 Four-Bit Adder Module -- Logic Diagram
C4
B4
P4
S4
A4
C3
B3
P3
S3
A3
C2
B2
P2
S2
A2
C1
B1
P1
S1
A1
C0
C0
(b)
SN7483 Four-Bit Adder -- Logic Equations
Pi = (BiAi)(Ai + Bi)
= (Ai + Bi)(Ai + Bi)
= Ai  Bi
(4.24)
i = Pi  Ci-1
= Ai  Bi  Ci-1
(4.25)
C1 = [C0(A1B1) + (A1 + B1)]
= [C0(A1B1)](A1 + B1)
= (C0+(A1B1))(A1 + B1)
= C0A1 + C0B1 + A1B1
(4.26)
Similarly
Ci = Ci-1Ai + Ci-1Bi + AiBi
Add Times for SN7483 Adder Circuits
SN7483 propagation delays
t1 = 3 tgate
t2 = t3 = t4 = 4 tgate
tC1 = tC2 = tC3 = tC4 = 3 tgate
SN7483-based Ripple-Carry Adder (n-bits)
tadd = (3m + 1) tgate
where m = n/4.
Fully Parallel Three-Bit Adder
c0 = x 0 y0
s0 = x0  y0
(4.30)
c1 = x1y1c0’+x1y1c0+x1y1’c0+x1’y1c0
= x1y1+(x1y1)c0
= x1y1+(x1y1)(x0y0)
s1 = x1y1c0
= x1y1 x0y0
(4.31)
c2 = x2y2+(x2y2)c1
= x2y2+(x2y2)[x1y1+(x1y1)(x0y0)]
= x2y2+(x2y2)(x1y1)+(x2y2)(x1y1)(x0y0)
s2 = x2y2c1
= x2y2[x1y1+(x1y1)(x0y0)]
(4.32)
Add Time for a Fully Parallel Adder
Assuming a three-level realization
tadd = 3 tgate
However, the fan in requirements become impractical
as n increases.
Carry Look-Ahead Adders -- Basic Idea
Recall that
ci = xiyi + xici-1 + yici-1
= xiyi + xiyici-1 + xiyici-1 + xiyici-1 + xi yici-1
= xiyi + xiyici-1 + xi yici-1
= xiyi + (xiyi + xi yi)ci-1
= xiyi + (xi  yi)ci-1
Let
gi = xiyi
[carry generate]
(4.33)
pi = xi  yi
[carry propagate]
(4.34)
Then
ci = gi + pi ci-1
si = pi  ci-1
(4.38)
Carry Look-Ahead Adders -- Three-Bit Example
c0 = g0
s0 = p 0
c1 = g1 + p1c0
= g1 + p1g0
s1 = p1  c0
c2 = g2 + p2c1
= g2 + p2(g1 + p1g0)
= g2 + p2g1 + p2p1g0
s2 = p2  c1
(4.35)
(4.36)
(4.37)
Carry Look-Ahead Adder Design
xi yi
ci
g2
gi
pi
g1
p2
si
c2
c1
(a)
(b)
x2 y2
x1
Adder
g2 p2
y1
x0
g1 p1
s1
g0 p0
CLA circuit
c2
0
Adder
Adder
s2
y0
c1
c0
(c)
Figure 4.39
s0
p1
g0
c0
Add Times for Carry Look-Ahead Adders
Adder modules
tg = tp = ts = tgate
CLA module
tc = 2 tgate
Overall
tadd = tgate + 2 tgate + tgate
= 4 tgate
Binary Subtraction Circuits
Recall that
(R)2 = (P)2 - (Q)2
= (P)2 + (-Q)2
= (P)2 + [Q]2
= (P)2 + (Q)2 + 1
For an SN7483 adder
()2 = (A)2 + (B)2 + (C0)2
where
(4.39)
 = 4321, A = A4A3A2A1, and B = B4B3B2B1
If C0 = 0, A = P, and B = Q, then ()2 = (P)2 + (Q)2 .
If C0 = 1, A = P, and B = Q, then ()2 = (P)2 - (Q)2 .
Two’s Complement Adder/Subtracter
Q = (q3 q2 q1 q0)2
P = (p3 p2 p1 p0)2
4A3A2A 1A 4B 3B 2B 1B
MUX (74157)
4Y 3Y 2Y 1Y
A4 A3 A2 A1
C4
Select
S
G
B4 B3 B2 B1
ADDER (7483)
C0
S4 S3 S2 S1
R = (r4 r3 r2 r1)2
Figure 4.41
Select
Function
0
R=P+Q
1
R=P+Q+1
Arithmetic Overflow Detection
an-1 bn-1 cn-2
cn-1 sn-1
V
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
Overflow Detection Circuits
an-1
cn-1
bn-1
FA
an-2
FA
cn-2
sn-1
V
bn-2
sn-2
(a)
an-1
cn-1
bn-1
FA
an-2
cn-2
sn-1
bn-2
FA
sn-2
V
(b)
Figure 4.42
cn-3
cn-3
B
Data acquisition
system
B1
Input sensor data
Top level
B2
Compute values
B3
Select output
Level 2
*
B1
Sensor
1
A
B1
Sensor
2
B
B2
A1+
B
B2
A2Ð
B
*
*
*
*
* = Leaf
node
B2
Min(A,
3
B)
B23
Compar
1
Ae&
B
*
(a)
B2
Level
3
Max(A,
4
B)
B23
B24
B24
Selec
2
t
Min
Compar
1
Ae&
B
Selec
2
Ma
t
x
*
*
*
Level
4
Sensor
s
B1 Ð
Input
B2 Ð
Computation
B1
A
Convert
1
A
B
Convert
2
B
B1
B2
Binar
1
adde
y
r
B2
Binar
2
subtracto
y
r
B23
Compar
1
e
B2
3
B23
Selec
2
t
B24
Compar
1
e
B24
Selec
2
t
B2
Minimum
Maximu
4
m
Functio
selec
n
t
ProcessBcontrol
system
Output
B3
select
Output
(b)
s1
s2
Decoders
y0
LSB
x0
y1
x1
n-to-2n
Decoder
MSB xn-1
y2n-1
Decoder Realization
LSB A
LSB A
m0
MSB B
m0
MSB B
m1
m1
m2
m2
m3
m3
(a)
(b)
m1
LSB A
m0
MSB B
m2
(c)
m3
C
B
A
More complex decoders
A
B
m0 = CBA
m1 = CBA
A
C
A
B
m2 = CBA
A
m3 = CBA
A
B
m4 = CBA
A
C
m5 = CBA
m6 = CBA
A
B
A
m7 = CBA
m0
m1
m2
m3
m4
m5
m6
m7
(b)
(a)
k0
C
m0
m1
m2
m3
m4
m5
m6
m7
m8
m9
m10
m11
m12
m13
m14
m15
k1
2-to-4
D
MSB
k2
k3
l1
l2
l0
l3
2-to-4
B
(c)
A
LSB
Example 4.1 -- Realize f(Q,X,P) =
m(0,1,4,6,7) = M(2,3,5)
0
P
X
Q
A
1
B
2
C
3
0
P
X
f(Q, X, P)
Q
A
1
B
2
C
3
4
4
5
5
6
6
7
7
(a)
f(Q, X, P)
(b)
Example 4.1 (concluded)
0
P
X
Q
A
1
B
2
C
3
0
P
X
f(Q, X, P)
Q
A
1
B
2
C
3
4
4
5
5
6
6
7
7
(c)
f(Q, X, P)
(d)
x0
y0
x1
y0
x0
y1
y1
x1
y2
y2
E
y3
y3
E
(a)
(b)
I0
x0
I1
x1
y0
O0
y1
O1
y2
O2
y3
O3
y0
O4
y1
O5
y2
O6
y3
O7
y0
O8
y1
O9
y2
O10
y3
O11
y0
O12
y1
O13
y2
O14
y3
O15
E
x0
x1
I2
x0
I3
x1
y0
E
y1
y2
1
E
y3
I0
x0
I1
x1
I2
E
x0
x1
y0
O0
y1
O1
y2
O2
x0
x1
E
y3
O3
y0
O4
y1
O5
y2
O6
x0
x1
E
E
y3
(a)
O7
(b)
G1
(6)
(4)
G2A
G2B (5)
(15)
(14)
(13)
A
B
C
(1)
Y0
Vc
c
16
Data
outputs
Y0
Y1
15
14
(2)
Y3
12
Y4
Y5
11
(3)
(10)
(9)
(7)
Y1
Y2
Y3
B
C
G2
A
G2
B
1
2
3
A
B
Selec
t
C
4
G2
A
5
G2
B
Enabl
e
(b
)
Y4
Y5
Y3
Y4
Y6
G1
Y7
6
7
8
G1
Outpu
Y7
t
GND
Y5
Y6
Y7
(a)
Input
Output
s
s
Enabl
Selec
e G2
t
G1 * C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H L L L L L H H H H H H H
H L L L H H L H H H H H H
H L L H L H H L H H H H H
H L L H H H H H L H H H H
H L H L L H H H H L H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L
´ H ´ ´ ´ H H H H H H H H
L ´
´ ´ ´ H H H H H H H H
G2* = G2A +
G2B
(c
)
9
Y2
A
(11)
Y6
10
Y1
Y0
(12)
Y2
13
'138
BIN/
0
1
2
3
4
5
6
7
A
B
C
G1
G2
A
G2
B
(d
)
(1)
A
(2)
B (3)
OCT
1
2
3
C
(6)
(4)
G1
G2 (5)
A
G2
B
&
E
N
(e
)
0
1
2
3
4
5
6
7
(15)
(14 Y0
) Y1
Y2
(13)
Y3
(12)
Y4
(11)
Y5
(10)
Y6
(9) Y7
(7)
G1
G2
0
1
2
3
4
Inputs
Outputs
VCC
5
24
23
22
21
20
19
18
17
16
15
14
A
B
C
D
G2
G1
15
14
13
12
13
6
A
7
0
11
B
8
1
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
10
11
C
9
1
D
10
11
12
13
14
15
AAB B C C DD
(a)
Outputs
(b)
12
GND
Inputs
G1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
G2
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
´
´
´
Outputs
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
´
´
´
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
´
´
´
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
´
´
´
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
10
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
11
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
12
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
13
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
(c)
'154
'154
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
C
D
G1
A
(23)
(22)
B (21)
C
(20)
(18)
(19)
G2
(d)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
4
8
D
G1
G2
BIN/OCT
&
EN
(e)
(1)
(2) 0
(3) 1
(4) 2
(5) 3
(6) 4
(7) 5
(8) 6
(9) 7
8
(10) 9
(11) 10
(13) 11
(14) 12
(15) 13
(16) 14
(17) 15
14
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
n-Bit address
S
Device 0
S
Device 1
y0
A0
x0
y1
A1
x1
É
AnÐ1
É
É
xnÐ1
E
y2nÐ1
Device access
control signal
S
Device 2nÐ1
S = select device
Z
Y
X
W
23
22
21
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
C
D
20
2
7408/4
7
10
4
18
17
9
10
12
7420/2
19
74154
f2 = PM(6, 9)
8
f1 = åm(1, 9, 12, 15)
14
13
G1
G2
6
5
0
1
BCD
input
D
2
C
3
B
4
A
5
6
(a)
7
8
9
Decimal
outputs
BCD code
DCBA
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Decimal digits
0
1
2
3
4
5
6
7
8
9
(b)
D
DC
BA
00
0
00
01
4
11
12
1
1
5
13
3
7
6
1
A
11
14
5
3
B
d
10
7
0
00
9
15
6
14
A
5
13
9
d
3
B
d
10
8
d
7
15
11
d
10
d
11
12
1
1
11
d
2
01
4
01
d
10
00
8
13
1
11
d
10
d
11
12
D
DC
BA
d
01
d
2
01
4
00
9
15
10
00
0
d
11
B
10
8
d
01
D
DC
BA
1
2
6
14
10
C
C
C
(b)
(c)
d
10
d
(a)
A
11
d
d
a
Ð
a
a
+
+
a
f
Ð
f
b
f
b
b
f
b
g
Common
anode
g
g
Common
cathode
g
e
e
c
e
c
c
e
c
d
d
d
(a)
d
(b)
A
AB
CD
00
0
00
1
1
01
5
3
13
7
15
1
00
1
01
D
14
d
5
13
7
1
9
d
15
1
6
1
10
8
d
0
1
2
10
11
12
1
1
3
C
10
d
1
11
d
01
4
1
11
d
0
00
0
9
d
1
6
1
10
8
d
1
1
2
10
11
12
0
0
11
C
01
4
A
AB
CD
1
14
0
B
B
(b)
d
10
d
(a)
D
11
d
d
A1
x3
0
4
d
1
12
1
5
0
8
d
13
d
1
9
d
d
X0
3
A0
X1
X2
7
d
4-to-2
Encoder
x1
2
A1
6
0
X3
15
d
14
d
x0
11
d
d
10
d
d
x2
(a)
A1 = X2 + X3
A0
X3
X3
X2
X1
X0
A1
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
d
0
0
d
1
d
d
d
1
d
d
d
d
d
d
d
d
0
1
d
0
d
d
d
1
d
d
d
d
d
d
d
0
4
d
1
5
0
3
13
7
2
1
9
d
15
d
6
1
8
d
d
d
X1
12
0
d
14
d
X0
11
d
d
10
d
d
X2
A0 = X1 + X3
(c)
(b)
X1
A0
X3
X2
A1
X3
(d)
A0
x4
0
4
12
8
5
13
9
3
7
15
11
2
6
14
10
1
1
x1
1
A0
x2
4-to-3
Encoder
x3
A1
x1
A2
x2
x4
(a)
x3
A1
x4
0
X4
X3
X2
X1
A2
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
4
12
8
1
A0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
x2
1
5
13
9
3
7
15
11
6
14
10
2
x1
1
x3
A2
x4
0
4
12
8
1
1
5
13
9
3
7
15
11
2
6
14
10
(b)
x2
x1
x3
x1
x3
x1
x3
x1
x3
x3
x2
(c)
x4
A0
x2
x1
x4
x3
x2
x4
x2
x4
A1
x2
x4
(d)
A2
x1
A1
x3
0
4
12
1
1
5
13
1
3
x0
7
x1
A1
x2
x1
2
10
1
x3
00
X2
X1
X0
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
(b)
1
A1 = X2 + X3
A0
X3
1
x2
(a)
Inputs
x0
11
14
GS
EO
1
1
1
x3
9
15
6
1
1
1
A0
4-to-2
Priority
encoder
8
1
Outputs
A0 GS EO
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
01
4
11
12
00
1
1
5
13
01
3
7
9
15
1
2
10
1
1
11
x1
10
8
1
6
14
1
x0
11
1
1
10
1
1
x2
A0 = X3 + X1X2
(c)
x1
x2
A0
x3
x2
A1
EO
x0
GS
(d)
Inputs
1
2
A
3
Outputs
1
2
3
4
5
6
7
8
9
H
´
´
´
´
´
´
´
´
L
H
´
´
´
´
´
´
´
L
H
H
´
´
´
´
´
´
L
H
H
H
´
´
´
´
´
L
H
H
H
H
´
´
´
´
L
H
H
H
H
H
´
´
´
L
H
H
H
H
H
H
´
´
L
H
H
H
H
H
H
H
´
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
D
C
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
B
H
H
H
L
L
H
H
L
L
H
A
H
L
H
L
H
L
H
L
H
L
(b)
4
B
5
Inputs
Vcc
NC
Output
D
16
15
14
13
12
11
10
D
3
2
1
9
6
3
2
1
9
Outputs
A
9
4
C
7
8
D
9
(a)
A
5
6
7
8
C
B
1
2
3
4
5
6
7
8
4
5
6
7
8
C
B
GND
Inputs
Outputs
(c)
0
EO
Inputs
EI
GS
H
L
L
L
L
L
L
L
L
L
1
2
A0
Outputs
0
1
2
3
4
5
6
7
´
H
´
´
´
´
´
´
´
L
´
H
´
´
´
´
´
´
L
H
´
H
´
´
´
´
´
L
H
H
´
H
´
´
´
´
L
H
H
H
´
H
´
´
´
L
H
H
H
H
´
H
´
´
L
H
H
H
H
H
´
H
´
L
H
H
H
H
H
H
´
H
L
H
H
H
H
H
H
H
3
A2 A1 A0 GS
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
L
EO
H
L
H
H
H
H
H
H
H
H
(b)
4
Outputs
A1
5
Inputs
Vcc
EO
GS
3
2
1
0
Output
A0
16
15
14
13
12
11
10
9
EO
GS
3
2
1
0
6
4
A0
5
6
7
El
A2
A1
1
2
3
4
5
6
7
8
4
5
6
7
E1
A2
A1
GND
A2
7
El
Inputs
(a)
Outputs
(c)
K-Channel multiplexing/demultiplexing
Multiplexer
Demultiplexer
Ain
Aout
Bin
Bout
SW1
Kin
SW2
Kout
Single
channel
(a)
Ain
Single
channel
a
Aout
a
Bin
Bout
b
É
b
Kin
Figure 4.22
É
Kout
k
k
(b)
Four-to-one multiplexer design
D0
D1
4-to-1
Multiplexer
D2
Y
D3
B
A
Selection code
(a)
B
A
Y
0
0
1
1
0
1
0
1
D0
D1
D2
D3
(b)
D0
D0
D1
D1
Y
Y
D2
D2
D3
D3
0 1 2 3
2-to-4
Decoder
B
A
(c)
B
A
(d)
Input
lines
First
level
I0
D0
I1
D1
I2
D2
I3
D3
Y
B
I4
D0
I5
D1
I6
D2
I7
D3
A
Y
Second
level
B
A
D0
D1
Y
D2
D3
I8
D0
I9
D1
I10
D2
I11
B
D0
I13
D1
I14
D2
I15
D3
A
S3
S2
Y
Selection code
(higher-order bits)
D3
I12
B
A
Y
B
A
S1
S0
Selection code
(lower-order bits)
Output line
Z
Data inputs
Data select
Inputs
Vcc
4
5
6
7
A
B
C
16
15
14
13
12
11
10
9
D4
D5
D6
D7
A
D3
Select
C
´
L
L
L
L
H
H
H
H
B
C
D2
D1
D0
Y
W
S
B
´
L
L
H
H
L
L
H
H
Outputs
Strobe
A
´
L
H
L
H
L
H
L
H
Y
G
H
L
L
L
L
L
L
L
L
L
D0
D1
D2
D3
D4
D5
D6
D7
W
H
D0
D1
D2
D3
D4
D5
D6
D7
(b)
'151A
1
2
3
4
5
6
7
8
0
3
2
1
0
Y
W
Strobe
G
GND
1
Data inputs
2
Outputs
3
(a)
Y
4
Strobe
enable
W
5
G
6
D0
7
G C B A
D1
(d)
D2
D3
Output Y
Output W
D4
G
A
B
D5
CÊ
D0
D6
D1
D7
D2
D3
A A B B C C
D4
A
D5
B
D6
D7
C
(c)
(7)
(11)
'151A
EN
0
(10)
(9)
(4)
(3)
(2)
(1)
(15)
(14)
(13)
(12)
G
0
7
2
0
(5)
1
(6)
2
3
4
5
6
7
(e)
Y
W
E7
E6
C
E5
E4
E3
E1
E2
E0
S
W
E3
D
E4
1
7
2
6
3
5
4
5
4
3
Data inputs
6
2
7
1
8
0
9
10
11
12
Strobe W
D GND
G Out- Data
put select
E5
E6
(a)
E7
W
E8
E9
Inputs
Select
D
´
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
´
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
´
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Output
A
´
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
(b)
Strobe
Output
G
W
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E10
E11
E12
E13
E14
E15
A A B BCCDD
A
B
C
D
(c)
'150
'150
(9)
E0
G
E1
(15)
A
(14)
B
(13)
C (11)
D
E2
E3
E4
E5
E6
E7
E8
W
E9
E10
E11
E12
E13
E14
E15
G
D C B A
(d)
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
EN
0
G
0
15
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(e)
(10)
W
Pair 0
1C0
2C0
Pair 1
1C1
2C1
1C2
2C2
Pair 2
1C0
1Y
Output
pair
2Y
Selection code
1C1
1C3
2C3
B
A(LSB)
Pair 3
0
2C0
2
(BA)2
1
2C1
1Y
1C2
2Y
2
2
2
2
C0
2
C1
Y
C2
C3
2C2
BA
1C3
3
2
2C3
Selection code
Position
(a)
(c)
(b)
'15
3
Strong 1G
(enable)
1C0
A
Output
1Y
1C1
Data 1
1C2
B
(14)
(2)
(1)
1G (6)
1C0 (5)
1C1 (4)
1C2 (3)
1C3 (15)
1C3
B
Select
A
2G (10)
(11)
2C0 (12)
2C1 (13)
2C2
2C3
2C0
2C1
Data 2
0
G
1
0
3
MUX
EN
0
1
(4)
3
(7)
2Y
Output
2Y
2C2
2C3
Strobe
(enable) 2G
(e)
(d)
1Y
2
Inputs
Inputs
Vcc
Strobe
4ZA
4B
Output
4Y
3A
3B
Output
3Y
16
15
14
13
12
11
10
9
G
4A
4B
4Y
3A
3B
Inputs
S
3Y
1A
1B
1Y
2A
2B
Strobe
G
H
L
L
L
L
2Y
1
2
3
4
5
6
7
8
Select
1A
1B
1C
Output
2A
2B
2Y
Output
GND
Inputs
Output
Select
Data
S
A B
´
´
´
L
L ´
L
H ´
H
´ L
H
´ H
Y
L
L
H
L
H
(b)
Inputs
(a)
1A
1Y
1B
'15
7
2A
2Y
2B
G
A/B
(15)
(1)
EN
G1
3A
3Y
3B
4A
4Y
4B
(2)
1A (3)
1B (5)
2A (6)
2B
3A (11)
3B (10)
4A (14)
4B (13)
MUX
1
(4)
(7)
(9)
Strobe G
(12)
Select S
(d)
(c)
1Y
1
2Y
3Y
4Y
Inputs
Inputs
Vcc
Strobe
4ZA
4B
Output
4Y
3A
3B
Output
3Y
16
15
14
13
12
11
10
9
G
4A
4B
4Y
3A
3B
Inputs
S
3Y
1A
1B
1Y
2A
2B
Strobe
G
H
L
L
L
L
2Y
1
2
3
4
5
6
7
8
Select
1A
1B
1C
Output
2A
2B
2Y
Output
GND
Inputs
Output
Select
Data
S
A B
´
´
´
L
L ´
L
H ´
H
´ L
H
´ H
Y
L
L
H
L
H
(b)
Inputs
(a)
1A
1Y
1B
'15
7
2A
2Y
2B
G
A/B
(15)
(1)
EN
G1
3A
3Y
3B
4A
4Y
4B
(2)
1A (3)
1B (5)
2A (6)
2B
3A (11)
3B (10)
4A (14)
4B (13)
MUX
1
(4)
(7)
(9)
Strobe G
(12)
Select S
(d)
(c)
1Y
1
2Y
3Y
4Y
4YÐ1Y
4YÐ1Y
4
4
D7ÐD4
Select
0=X
1=W
D3ÐD0
8
D7ÐD0
Destination
(a)
Source M Source N
D3ÐD0
D3ÐD0
4
4
4AÐ1A
4Y
4BÐ1B
G
74157
S
3Y 2Y 1Y
Source O
D3ÐD0
4
Source P
D3ÐD0
4
4AÐ1A
4BÐ1B
G
74157
S
4Y 3Y 2Y 1Y
S0 S1
D3
D2
D1
Destination
D0
(b)
S0
0
0
1
1
S1 Source
0
M
1
N
0
O
1
P
Use a 74151A multiplexer to Realize
f(x1,x2,x3) = m(0,2,3,5)
VCC
74151A
i
0
1
2
3
4
5
6
7
C B A
x1 x2 x3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y
f
1 D0 = 1
0 D1 = 0
1 D2 = 1
1 D3 = 1
0 D4 = 0
1 D5 = 1
0 D6 = 0
0 D7 = 0
(a)
D0
D1
D2
D3
D4
Y
D5
W
D6
D7
G
C B A
x1 x2 x3
Selection code
(b)
Figure 4.30
f(x1, x2, x3)
a b
0
0
1
1
0
1
0
1
f(a, b, c)
MUX Inputs
c
0
c
1
D0 = c
D1 = 0
D2 = c
D3 = 1
c
D0
0
D1
c
D2
1
D3
f(a, b, c)
Y
B A
(a)
a b
Selection code
(b)
b c
0
0
1
1
0
1
0
1
f(a, b, c)
MUX Inputs
0
1
a
a
D0 = 0
D1 = 1
D2 = a
D3 = a
(c)
0
D0
1
D1
a
D2
a
D3
f(a, b, c)
Y
B A
b c
Selection code
(d)
C B
i
0
1
2
3
4
5
6
7
A
Y
X1 X2
X3
X4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
f
f
1
1
1
1
1
1
1
0 X4
0
0
0
0
1 X4
0
0
0
0
1 X4
1
1
1
(a)
x4
VC
C
74151A
D0 = 1
D1 = 1
D0
D1
D2
D2 = X4
f(x1, x2, x3, x4)
D3
D4
D3 = 0
Y
W
D5
D6
D4 = X4
D5 = 0
D7
G
C BA
D6 = X4
x1 x2 x3
D7 = 1
Selection code
(b)
Input
D
E
Y0
Enable
Input
1-to-n
Demultiplexer
É
Y0
Y1
Y1
Y2
Outputs
Y3
YnÐ1
1
m0 m1 m2 m3
2-to-4
Decoder
É
2
S
Selection
code
(a)
B
A
Selection
code
(b)
x0
x1
x2
x3
x4
x5
x6
x7
x8
x9
x10
x11
x12
x13
x14
x15
16 lines
8
7
6
5
4
3
2
1
23
22
21
20
19
18
17
16
9
E0
E1
74150
E2
E3
E4
E5
E6
E7
E8
Multiplexer
Y
10
E9
E10
E11
E12
E13
E14
E15
G DC
11
B A
13 14 15
1
0
2
74154
1
3
2
4
3
5
Single data
4
channel (Q)
6
5
7
6
8
7
Decoder/ demultiplexer
9
8
18
10
9
G1
11
10
13
11
G2
14
19
12
15
13
16
14
17
D C B A 15
20
C3
C2
C1
C0
5 lines
21 22 23
x0
x1
x2
x3
x4
x5
x6
x7
x8
x9
x10
x11
x12
x13
x14
x15
A2
B2
S2
GND
C2
NC
NC
14
13
12
11
10
9
8
C0
S2
B2
A2
A1
C2
S1
B1
S1
A1
B1
1
2
3
S1
A1
B1
C0
4
5
6
7
VCC
C0
NC
NC
C1
(a)
Inputs
Outputs
When C0 = L
When C0 = H
A2 A1
B2 B1
C2 S2 S1
C2 S2 S1
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
L
H
L
L
H
H
L
H
H
H
L
L
L
H
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
(b)
L
L
H
H
L
H
H
L
H
H
L
L
H
L
L
H
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
H
L
H
H
L
L
H
L
L
H
L
L
H
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
S2
B2
A2
C2
(c)
B4
S4
C4
C0
GND
B1
A1
S1
16
15
14
13
12
11
10
9
S4
C4
C0
B1
B4
A1
S1
A4
A2
S3
A3
B3
1
2
3
4
A4
S3
A3
B3
(a)
S2
B2
5
6
7
8
VCC
S2
B2
A2
C4
B4
P4
S4
A4
C3
B3
P3
S3
A3
C2
B2
P2
S2
A2
C1
B1
P1
S1
A1
C0
C0
(b)
ci
yi
xi
gi
si
pi
g1
p2
g2
c1
c2
(b)
(a)
g2
Adder
Adder
Adder
g1
p2
g0
p1
CLA circuit
c2
c0
c1
(c)
p0
s0
s1
s2
0
y0
x0
y1
x1
y2
x2
p1
g0
c0
Inputs
Outputs
Vcc
P2
G2
Cn
Cn+x
Cn+y
G
Cn+z
16
15
14
13
12
11
10
9
P2
G2
Cn
Cn+x
Cn+y
G
G1
1
G1
Cn+z
P1
G0
P0
G3
P3
P
2
3
4
5
6
7
8
P
GND
P1
G0
P0
G3
P3
Inputs
Output
(a)
Inputs
Output
Inputs
Output
G3 G2 G1 G0 P3 P2 P1
G
P3 P2 P1 P0
P
L
L
L
L
H
L
L
L
´
´
´
´
L
´
´
´
´
L
´
´
´
´
L
´
´
´
´
L L ´
L L L L
All other combinations
´
L L L
All other
combinations
(c)
(b)
Output
Inputs
G0 P0
L
´
Cn
Cn+x
´
H
H
´
L H
All other
combinations
H
Output
Inputs
G1 G0 P1 P0
L
´
´
´
L
´
L
Cn
Cn+y
´
´
H
H
H
L
´
´
L L H
´
All other combinations
L
(d)
(e)
Output
Inputs
G2 G1 G0 P2 P1 P0
L
´
´
´
´
L
´
´
´
´
L
´
´
L
´
´
´
´
Cn
Cn+z
´
´
´
H
H
H
H
L
L L ´
L L L H
All other combinations
(f)
P or X
G or Y
P3 or X3
G3 or Y3
Cn+z
or
Cn+z
P2 or X2
G2 or Y2
Cn+y
or
P1 or X1
G1 or Y1
Cn+y
Cn+x
P0 or X0
G0 or Y0
or
Cn+x
Cn or Cn
(g)
Q = (q3 q2 q1 q0)2
P = (p3 p2 p1 p0)2
4A3A2A 1A 4B 3B 2B 1B
MUX (74157)
4Y 3Y 2Y 1Y
A4 A3A2 A1
C4
Select
S
G
B4 B3 B2 B1
ADDER (7483)
S4 S3 S2 S1
R = (S4 S3 S2 S1)2
C0
Select Function
0
R=P+Q
1
R=P+Q+1
anÐ1
cnÐ1
bnÐ1
FA
anÐ2
É
FA
cnÐ2
snÐ1
V
bnÐ2
cnÐ3
snÐ2
(a)
anÐ1
bnÐ1
anÐ2
bnÐ2
cnÐ2
FA
É
FA
cnÐ3
cnÐ1
snÐ1
snÐ2
V
(b)
i
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
f1, A < B
2
A
Magnitude
comparator
B
f2, A = B
2
f3, A > B
(a)
A1
A0
B1
B0
f1
f2
f3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
(b)
A1
f1, A < B
0
4
12
A1
f2, A = B
8
0
4
12
8
13
9
1
1
5
13
9
1
5
1
3
1
7
1
B1
2
15
6
1
B0
11
1
3
7
15
1
14
B0
11
1
B1
10
2
6
14
1
10
1
A0
A0
A1
f3, A > B
0
4
12
1
1
5
8
1
13
1
9
1
B1
3
7
15
2
6
14
11
10
1
A0
(c)
1
B0
A1
f3
B1
A0
f1
B0
f2
A<B A=B
In
In
A>B
In
A>B
Out
A=B A<B
Out
Out
1
2
3
4
5
6
7
8
B3
Data
input
A<B
In
A=B
In
A>B
In
A>B
Out
A=B
Out
A<B
Out
GND
Cascade inputs
Cascade outputs
(a)
Comparing
inputs
A3, B3
A2, B2
A3 > B3
´
A3 < B3
´
A3 = B3
A2 > B2
A3 = B3
A2 < B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
A3 = B3
A2 = B2
Cascading
inputs
A1, B1
A0, B0
´
´
´
´
A1 > B1
A1 < B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
´
´
´
´
´
´
A0 > B0
A0 < B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
Outputs
A>B A<B A=B
´
´
´
´
´
´
´
´
H
L
L
´
H
L
(b)
´
´
´
´
´
´
´
´
L
H
L
´
H
L
´
´
´
´
´
´
´
´
L
L
H
H
L
L
A>B A<B A=B
H
L
H
L
H
L
H
L
H
L
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
A3
B3
A>B
A2
B2
A<B
A=B
A=B
A>B
A1
B1
A<B
A0
B0
(c)
0 1 0
c3 c2 c1
B0
A0
B1
A1
B2
7485
A2
B3
A3
f3
f2
f1
Cascaded inputs
c3 c2 c1
B4
A4
B5
A5
7485
B6
A6
4
Data
A
c1
Cascade
inputs
c2
c3
Data
7485
B7
A7
A<B
f1
A<B
A=B
f2
A=B
A>B
f3
A>B
B
f3
f2
f1
Cascaded inputs
c3 c2 c1
B8
A8
4
B9
(a)
A9
B10
7485
A10
B11
A11
f3
f2
f1
Cascaded inputs
c3 c2 c1
B12
A12
B13
A13
B14
7485
A14
B15
A15
(b)
f1
A<B
f2
A=B
f3
A>B
Circuit
outputs
ai
bi
CiÐ1
S2
Ci
ALU
S1
S0
fi
(a)
anÐ1
bnÐ1
CnÐ1
a1
CnÐ2
b1
C1
a0
b0
C0
CÐ1
C-GEN
ALU
ALU
ALU
S2
S1
S0
fnÐ1
f1
(b)
f0
ai
bi
CiÐ1
x
y
x
LU
y
cin
AU
cou
t
f
f
S1
S0
Ci
fLUi
fAUi
x1
x0
MUX
y
fi
s
S2
x1
x0
s
y
x
y
x0
x1
x2
x3
MUX
y
s0
S0
s1
S1
f
(a)
S1
S0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
y
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FLU
0
0 x AND y
0
1
0
1 x OR y
1
1
1
1 NOT x
0
0
0
1 x XOR y
1
0
(b)
x
y
s1
s1s0
s0
xy
00
0
00
4
0
1
01
12
5
3
1
9
1
15
1
6
0
8
13
7
10
0
1
1
2
11
0
0
11
10
01
1
11
0
14
1
0
10
1
0
(c)
f
(d)
S1
S0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
bi
yi
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1
Add
Subtract
Increment
Decrement
(a)
bi
S1S0
00
bi
0
0
2
0
1
1
01
6
1
3
1
11
4
1
7
0
S1
10
0
5
1
S0
0
(b)
yi
(c)
S1
S0
0
0
1
1
0
1
0
1
CÐ1
0
1
1
0
Add
Subtract
Increment
Decrement
(a)
S1
0
S0
1
0
0
2
0
1
1
1
CÐ1
3
1
0
S1 S0
(b)
(c)
ai
bi
Y-GEN
S1
S0
CiÐ1
LU
fLU
i
FA
AU
fAU
i
Ci
S2
MUX
f
i
Storage
register
Adder
Module: SR
Keypad
input
Module: FA4
Display
driver
gnd
a0
add0
Module:
FA1
a1
a2
s0
a3
b0
add1
Module:
FA1
s1
add2
Module:
FA1
s2
add3
Module:
FA1
s3
FA4
Module
design
b1
b2
b3
N,C.
a
b
X1
x1
X2
s
cin
A1
A2
A3
FA1
Module
design
a1
a2
a3
R1
cou
t
Module: FA1
a
s
b
cou
t
cin
(a)
Hierarchical
connectors
a
b
X1
x1
X2
s
cin
A1
A2
A3
a1
a2
a3
(b)
R1
cou
t
A(3:0)
B(3:0)
A(0)
A0
A(1)
A1
A(2)
A2
A(3)
A3
S(3:0)
S0
S1
FA4
S2
B(0)
B0
S3
B(1)
B1
B(2)
B2
B(3)
B3
S(0)
S(1)
S(2)
S(3)
(a)
A(3:0)
Pin A(3:0)
S(3:0)
Pin S(3:0)
B(3:0)
Pin B(3:0)
FA4
(b)
Time
0
5
7
10
12
a(3:0)
0000
0110
0110
0110
0110
b(3:0)
s(3:0)
0000
0101
0101
0001
0001
0000
0000
1011
1011
0111
(a)
a(3:0)
0000
b(3:0)
0000
s(3:0)
0000
0
0110
0101
0001
1011
5
10
Time
(b)
0111
15