Transcript What is ASIC? - London South Bank University

What is ASIC?
Application Specific Integrated Circuit.
An Integrated Circuit is called an ASIC if it is
designed for a specific application.
Example: UART, LCD controller, Coder/Decoder (CODEC)
Terminology
• Logic Cell any component of a Digital System
e.g. Logic Gate, Memory, Logic sub-system (on FPGA)
• Base Cell a small sub-circuit formed by a
predefined pattern of transistors
e.g. Current source, Current mirror, AND gate
ASIC types
How much of resources pre-defined on IC ?
• Full Custom ASIC nothing
• Gate Array ASIC Base Cells
• Standard Cell ASIC Logic Cells Library
Gate Array ASIC
Only the transistors are predefined in the
silicon wafer.
The predefined pattern of transistors on the
gate array is called a base array and the
smallest element in the base array is called a
base cell.
The base cell layout is same for each logic cell,
only the interconnect between the cells and
inside the cells is customized.
Full-Custom ASIC
The designer designs all or some of the logic
cells and the layout for that one chip.
The designer does not used predefined gates
in the design.
Every part of the design is done from scratch.
Standard Cell ASIC
The designer uses predesigned logic cells such as AND
gate, NOR gate, etc. These gates are called Standard
Cells. The advantage of Standard Cell ASIC’s is that the
designers save time, money and reduce the risk by
using a predesigned and pre-tested Standard Cell
Library. Also each Standard Cell can be optimized
individually. The Standard Cell Libraries is designed
using the Full Custom Methodology, but you can use
these already designed libraries in the design. This
design style gives a designer the same flexibility as the
Full Custom design, but reduces the risk.
Overview of ASIC Flow
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Requirements analysis by a team of design engineers
HDL description of an ASIC , usually in RTL (Register transfer level) design.
Functional verification Suitability for purpose is verified by.
Logic synthesis transforms the RTL design into a large collection of lower-level constructs
called standard cells. These constructs are taken from a standard-cell library consisting of precharacterized collections of gates (such as 2 input nor, 2 input nand, inverters, etc.). The
standard cells are typically specific to the planned manufacturer of the ASIC. The resulting
collection of standard cells, plus the needed electrical connections between them, is called a
gate-level netlist.
Placement The gate-level netlist is processed by placing the standard cells onto a region
representing the final ASIC.
Routing tool uses netlist to create electrical connections between standard. The output is a
file which can be used to create a set of photo masks enabling a semiconductor fabrication
facility (commonly called a 'fab') to produce physical ICs.
Static timing analysis Given the final layout, circuit extraction computes the parasitic
resistances and capacitances. In the case of a digital circuit, this will then be further mapped
into delay information, from which the circuit performance can be estimated.
Design rule checking This, and other final tests such as and power analysis (collectively called
signoff) are intended to ensure that the device will function correctly over all extremes of the
process, voltage and temperature. When this testing is complete the photomaps information
is released for chip fabrication.
Design Objectives
Speed - IC technology ,layout
Area
- IC technology, layout, complexity
Power -IC technology, complexity
Time to Market - IC technology, Design Flow
FPGA vs. ASIC Design Advantages
ASIC vs. FPGA Design Advantages
FPGA vs. ASIC Design Flow Comparison