Transcript Slide 1

PT module design and readout
Work in Progress
The concept does not have to be fully accurate but a concrete picture is
needed to expose the major issues and allows to propose solutions which can
be evaluated quantitatively
Geoff Hall
Overall layout [Mark P]
• Assume stacked layer at R ≈ 25 cm
– Tilted to minimise cluster size
R = 25cm
thickness = 285µm
• large clusters from grazing incidence
– need to simulate low pT tracks
– efficiency bias for oppositely charged
low pT tracks?
relevant if full readout for tracking is used?
Feb 2009
G Hall
R [cm]
pT_graze [MeV/c]
10
60
25
150
35
210
50
300
100
600
2
Occupancy estimates
• Scenarios for sLHC and vLHC W Scandale & F Zimmerman
– Nuclear Physics B (Proc. Suppl.) 177–178 (2008) 207–211
• 40MHz, peak luminosity 1.55x1035
– <294 interactions/bx>
– PYTHIA & total sinelastic(pp) = 79mb -> <306 interactions/bx>
• Then geometry dependent
– R = 25cm |h|=2.5, untilted sensors, 100um x 2.5mm pixels
– average occupancy over layer is 0.45% ± 17%[3s Poisson variation],
• cross section uncertainty = ±30%[Tomalin], low pt track uncertainty =
±12%[Tomalin], cluster width uncertainty = ±50%[simulation] => (0.45
± 0.3)% occupancy.
– Other factors include fluctuations in jets – being studied
Feb 2009
G Hall
3
PT layer pixel size
• Should reduce need to compare many nearby columns
– D independent of h, but offset in z between layers increases with h
• R-f: compare to assembly precision ~ 100µm
R = 25cm, L =28cm d = 2mm ∆ ≈ 2 mm
d
∆
∆
d
∆ = dL/R
R
R
q
Luminous region L
q’
L
LHC luminous region L ≈ 28cm (±3s) – may be larger or smaller at SLHC
Feb 2009
G Hall
4
Schematic PT module
Correlator
R = 25cm
Occupancy ~ 0.5% at 40MHz & 1035
-This is believed to be worst case
Data out
104
2
128 xx100µm
12.8mm
x
2x2.5mm
data
2 x 2.5mm
Inexpensive prototyping, using wire bonding, might be possible
- experimental demonstration will be important
Feb 2009
G Hall
5
PT layer readout
column of
128 pixels
• Bring data for comparison with second layer,
using minimum power
– high speed shift register? 128/25ns = 5.12Gb/s
• try to exploit low occupancy?
• address hit channels?
– 128 = 7 bits
– and should handle some multiple hits
• high PT candidates should be narrow clusters
– ignore clusters of 3 or more strips
– likely to be only one candidate group per 128 channel
even in congested environment
Feb 2009
G Hall
6
Possible schematic
column of
128 pixels
• divide column into 32 x 4 channel groups
–
–
–
–
eg logic sets 9 address lines:
5 bit group + 4 bit pattern +1 bit spare
provide more information than single channel address
ignore combinations consistent with wide clusters
• a moderate number of address lines could be
sufficient
– still plenty of space for power, clock, I2C, …
• probably share some in 256 channel chip
– Nearest neighbour logic to avoid group boundaries
• including (upper) chip edge
Feb 2009
G Hall
7
Some details
column of
128 pixels
• Valid 4 bit patterns
– 0001 0010 0100 1000 … 0011 0110 1100 …
– 1011 1101 = double cluster
• Invalid
– 0000 1111 1110 0111
• Although infrequent, there will be adjacent
groups – nearest neighbour logic to merge
– eg
0001 1100
is an invalid cluster
• Could also increase address lines to cope
– eg 110 groups of 8 channel groups => 12 bits
– cf 32 groups of 4 channels => 10 bits
• Optimise design using MC
– eg 256 elements, longer groups, and to avoid bias
Feb 2009
G Hall
8
More details
• At central boundary need data from ROC-L & ROC-R
– extra level of bonding?
[pixel:127]
[pixel:0]
ROC-L
ROC-R
ROC-L
ROC-R
Simplest solution:
If a valid pattern with hit in [pixel:127]
pass all data from last pixel, even if match not found
use spare bit as indicator that no matching comparison
extra data volume, for rejection factor 20
(1 + 127*0.05)/(128*0.05) ≈ 1.15
Feb 2009
G Hall
9
Data rate for PT module
Module 25.6mm x 80mm
256 x 32 sub-units = 8192 channels
Correlator Occupancy ~ 0.5% => 40 hit channels
PT reduction ≈ 20 [Mark P]
=> 2 hit channels/BX ≈ 32 bits, with column
address
Data out
104
2
128 xx100µm
12.8mm
x
2x2.5mm
data
2 x 2.5mm
Feb 2009
G Hall
10
ROC-1: 128 chan
ROC-2: 128 chan
ROC
Height: 128 x 100µm = 12.8mm +…
Width: 2 x 1.5mm = 3mm +
Space for bond pads, etc….
Dense bonds on module : 8192 channels
Optimised pitch size?
Max chip size in 130nm: 19.5mm x 21mm
Functions: amplifier, threshold adjustment, comparator,
latch, neighbour logic, connect to bus, internal test?
Questions
could assembly be done using inexpensive bump
bonding?
eg C4 layout with 200µm spacing should be possible
Power transmission over long, narrow chip?
Feb 2009
G Hall
11
Module - plan view of section
upper layer
lower layer
column
column
128
channels
128
channels
10 bit bus
10 bit bus
assembler
x10
x10
x10
x10
x10
x10
x10
x10
multi-via
Feb 2009
x10
store +
x10
x10
x10
assembler
x10
x10
(memory
buffer for
full
readout)
10 bits from column above
transmits column to each neighbour
receives 10 inputs from each neighbour
and stores
receives 10 inputs from module below
compares pattern from module below with
three (10 bit) stored patterns
interconnect
chip
G Hall
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Module - section view in r-f plane
assembler
ROC
PCB
2mm
sensor
ROC
store
PCB
Sensor & ROC
~ 200µm thick
Interconnect chip
mass produced, cheap
coarse pitch ~250µm
~2.5mm x 2.5mm
Maybe an easier method?
Very small component, with regular spacing -…
Feb 2009
G Hall
13
Possible connectors
O Zorba
Fine Stack
.40 mm Pitch Plug & Receptacle
Number of Positions = 80 (also 20,24,46,50,60)
Overall length = 18.4mm
Board-Board Stack Height = 1.0mm (X)
In-Line Contact Layout
Feb 2009
G Hall
X
14
Fine Stack socket
Feb 2009
G Hall
15
More speculative
… become more cost-effective at
board separations of about 0.200”
(5 mm) or less and pad pitches
below 0.050” (1.27 mm).
• Elastomeric connectors
Lifetime, aging, precision, reliability?
Feb 2009
G Hall
16
Module - section view in r-f plane
assembler
ROC
PCB
2mm
sensor
ROC
store
PCB
Sensor & ROC ~ 200µm thick
2.2mm
lateral connections via PCB layers and wire bonds
Questions:
what is achievable precision?
could all connections be made simultaneously?
what accuracy vertical spacing is required?
thermal stress
Feb 2009
G Hall
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Adapt module for bump bonding - r-f plane
wire bonding should be sufficient but could use silicon
interconnect bridge to connect ROCs laterally
sensor
ROC
assembler
PCB
store
PCB
2mm
ROC
An alternative variant with one layer inverted allows to avoid connectors but at the
price of having doubled sided modules and possible assembly and handling
questions.
How difficult will it be to align?
For all designs, what is the best cooling method? Pipes at module edge may be
sufficient
NB expect to remove material from “picture frame” under sensor
Feb 2009
G Hall
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ROC-2: 128 chan
ROC-1: 128 chan
Assembler
ROC (2)
Height: 128 x 100µm = 12.8mm +…
Width: 2 x 1.5mm = 3mm +
Space for bond pads, etc….
Dense bonds on module : 8192 channels
Optimised pitch & pixel size?
Max chip size in 130nm: 19.5mm x 21mm
Would be natural to make assembler part of ROC
and, if possible, aim for identical chip for top and
bottom layer
Height = 5mm ? => 18 mm x 6mm
Feb 2009
G Hall
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Assembler
• Identical chip for top and bottom layer possible?
10 x 10(?) µm
10 x 200µm
10 x 10(?) µm
10 x 10µm
10 x 200µm * Comparison logic – with
compensation for r-f offset (switch off
for lower layer)
* Time stamp & pattern buffer for 256
latency (if needed) –
5mm
10 x 200µm
10 x 10µm
10 x 200µm
1.5mm
10 x 100µm
staggered
Feb 2009
Logic
3 x 10 bit storage
1 x 10 bit from paired layer
10 x 100µm
staggered
G Hall
> 50% empty for O ≈ 0.5%
* Output 10 bit column to/from paired
layer (switch off for lower layer)
* Output pattern & address if
coincidence
* Need to receive/transmit clock
Dimensions from pad layout
20
Module – sensor above
concentrator
data out
control in
25.6mm
80mm
Is it feasible to assemble modules in this orientation?
(Connectors are below board in top layer)
Feb 2009
G Hall
interconnect bridges
( if bump bonds needed)
21
Module – sensor below
concentrator
data out
control in
25.6mm
80mm
Modularity: 10 bit bus = 320 lines, 4 x 80 way connectors
4 x 80 way =>4 x 18.4mm = 73.6mm
Feb 2009
G Hall
interconnect bridges
22
Module at large h – schematic plan view
eg
10mm
If accurate alignment possible, simply offset connectors, and add routing
Feb 2009
G Hall
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Comparison logic
• Modules are flat, not arcs
• z offset h dependent
• Compensate for Lorentz drift
• search window to allow for luminous region
• Orientation of module
and quantization => 3 pixels (if not tiny)
=> position dependent logic
[Anders/Mark P]
p=∞
~200µm
~12mm
h = 2.5
R-f view
z view
Luminous region
IP
NB position dependent logic could contribute to alignment – at expense of complexity
Feb 2009
G Hall
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Data transport
Control, PLL,
Trigger
Concentrator
26
27
28
29
30
31
to GBT
From 32 ROC + Assemblers & 0.5% occupancy
10 data bits + 5 address bits to transmit (differential?)
~2 hits/module to transfer/BX after PT match ≈ 1 hit/32 ROC
8 data bit bus + 1 busy bit @ 80Mb/s ?
Power - two arguments: CMOS logic [Mark] or energy per bit [Sandro]
(i) 2µW/MHz/cm x 80MHz x 8cm x 8 / 4096 = 2.5 µW/channel
(ii) 10pJ/bit x 16bit /25ns /4096 ≈ 1.6 µW/channel
Clock distribution?
Store data on assembler while awaiting readout
Feb 2009
G Hall
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Data volumes and link requirements
Assume 16 bits/chip to transfer
and trigger data from one layer
Options – following trigger
for 40M channels in stacked layer
(1)no further readout
Channels/chip
128
Occupancy
0.005
PT data reduction
0.050
Channels above PT cut/BX/layer
5,000
Bits/channel
No links @ 3.2Gbps [new]
16
1000
Power/link [W]
2.0
Link Power [kW]
2.0
Power/chan [µW]
50
Feb 2009
(2) read out unmatched patterns saved in
Assembler
(choose top or bottom layer)
more power: logic & to send data
more links and traffic management
extra data volume for rejection factor 20
≈ (40MHz/20 + 100kHz)/(40MHz/20) = 1.05
(3) read out all data
requires 6.4µs storage on each FE pixel
memory in ROC FE
significant extra power penalty & complexity
G Hall
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Power estimate
• Budget for PT layer: <120µW/chan using 130nm CMOS
– Front end
30µW (amp, threshold, logic, data transfer)
– GBT Links
50µW (not on module)
– Control, PLL 10µW [*]
– Digital logic
250µW x 64/8192 = 2µW (guess)
• little logic in pixel, comparison logic and data transfer on assembler
– Data transfer 2.5µW
– Data transfer to remote GBT @ 160Mbps [ref: B Meier]
2hits x 16 bits x 10pJ/bit x 160Mbps x 2m = 102mW/8192 = 12.5µW
Total:
107µW/channel ≈ 0.6 W/module locally (exc link)
Option (2): increase by ~ 5% => 112µW/channel
Option (3): for full readout => ??
* Ancillary chips in present tracker typically required 50mW => 20mW in 130nm
Assume one PLL per side => 20mW/(32*128) = 5µW
Feb 2009
G Hall
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Approximate dimensions
For stacked layer (doublet)
Pixel size
100µm x 2.5mm
ROC
2 x 128 channels
<Power>/pixel
120µW
|hMAX|
2.5
R
[cm
]
L
A
[m] [m2]
Nface Nchan
NROC
Nmodule
Nlinks
P
[kw]
25
3.0
64
150k
4700
960
4.6
9.6
38.5M
35
4.2 18.7 88
75M
293k 9200
1875
9.0
NB no allowance for overlaps in R-f or h
≈ number of APV25s
Simulations use 0.5-1mm overlap in f -> +8% [Mark P]
produced and tested
for present Tracker
Feb 2009
G Hall
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Conclusions
• The crucial issue is the assembly & interconnect problem
– do layers need to be precisely aligned – ie sub-100µm?
– is it feasible to use connectors?
• Density of lines on module and connections to sensors
suggest bump bonding will be required
– but “inexpensive” C4 looks feasible
• Power consumption for layer is still dominated by data
transmission off the detector
– this is very sensitive to occupancy and rejection factor
– it probably will be remote from module
Feb 2009
G Hall
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