Transcript Emerging Research Logic Devices1 PIDS ITWG Emerging New

ITRS ERD/ERM ITWG
Working Group FxF Meeting
Maturity Evaluation for Selected
Emerging Research Memory Technologies
Jim Hutchby and Mike Garner - Facilitating
Casa Don Guanella – Sala Rossa Room
Barza di Ispra (Varese Provence), Italy
Wednesday April 7, 2010
9:00 a.m. – 6:30 p.m.
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Work in Progress --- Not for Publication
Emerging Research Devices Working Group

Hiroyugi Akinaga
 Tetsuya Asai
 Yuji Awano
 George Bourianoff
 Michel Brillouet
 Joe Brewer
 John Carruthers
 Ralph Cavin
 U-In Chung
 Philippe Coronel
 Shamik Das
 Erik DeBenedictis
 Simon Deleonibus
 Kristin De Meyer
 Michael Frank
 Christian Gamrat
 Mike Garner
 Dan Hammerstrom
 Wilfried Haensch
 Tsuyoshi Hasegawa
 Shigenori Hayashi
 Dan Herr
 Toshiro Hiramoto
 Matsuo Hidaka
 Jim Hutchby
 Adrian Ionescu
 Kohei Itoh
 Kiyoshi Kawabata
 Seiichiro Kawamura
 Rick Kiehl
 Hiroshi Kotaki
AIST
Hokkaido U.
Fujitsu
Intel
CEA/LETI
U. Florida
PSU
SRC
Samsung
ST Me
Mitre
SNL
LETI
IMEC
AMD
CEA
Intel
PSU
IBM
NIMS
Matsushita
IBM
U. Tokyo
ISTEK
SRC
ETH
Keio U.
Renesas Tech
Selete
U. Minn
Sharp
Atsuhiro
Kinoshita
 Franz Kreupl
 Nety Krishna
 Zoran Krivokapic
 Phil Kuekes
 Lou Lome
 Hiroshi Mizuta
 Murali Muraldihar
 Fumiyuki Nihei
 Dmitri Nikonov
 Wei-Xin Ni
 Ferdinand Peper
 Yaw Obeng
 Dave Roberts
 Kaushal Singh
 Sadas Shankar
 Thomas Skotnicki
 Satoshi Sugahara
 Shin-ichi Takagi
 Ken Uchida
 Yasuo Wada
 Rainer Waser
 Franz Widdershoven
 Jeff Welser
 Philip Wong
 Kojiro Yagami
 David Yeh
 In-Seok Yeo
 In-K Yoo
 Peter Zeitzoff
 Yuegang Zhang
 Victor Zhirnov
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Toshiba
Qimonda
AMAT
AMD
HP
IDA
U. Southampton
Freescale
NEC
Intel
NDL
NICT
NIST
Air Products
AMAT
Intel
ST Me
Tokyo Tech
U. Tokyo
Toshiba
Waseda U.
RWTH A
NXP
NRI/IBM
Stanford U.
Sony
SRC/TI
Samsung
SAIT
Freescale
Intel
SRC
Work in Progress --- Not for Publication
Objectives
 Workshop
(for each of the nine technologies)
– Receive expert inputs (pro & con)
– Clarify status, potential, and remaining challenges
– Formulate discussion/decision points to be
considered in the Wednesday ERD/ERM memory
technology assessment meeting
 Emerging Research Devices Working Group Mtg.
– Discuss and reach approximate consensus on
potential & challenges for each technology
– Reach approximate consensus on any “New
Memory” technologies sufficiently mature to
benefit from accelerated development
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Evaluation Criteria
(Must Have) (1/2)
Potential for scaling beyond the 16nm generation
– What is the limit of scaling and limiting factor?
– Are there intrinsic statistical fluctuations that
could limit scaling*?
How well is the switching physics understood?
CMOS Compatibility?
*Large statistical fluctuation in the density of “tokens” for the state
–Example: 1018 vacancies/cm-3 is ~0.25 vacancies in a cell of a 16nm
technology with a 1nm thick active region
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Evaluation Criteria
(Important) (2/2)
 Minimum number of mask layers or photolith steps to fabricate
the device? (Cross bar is the minimum).
 Means of fabricating a crossbar array and related circuits.
– Potential for multiple bits per memory layer
– Potential for 3D integration of multiple memory layers
 How well are the materials and processes understood?
 Operating voltage
 Retention time of the state
 Amount of energy to change the memory state
 Ultimate time constant for changing the state
 Number of memory cycles
 Parasitic properties that may limit the technology (leakage
current, capacitance, etc)
 Low sensitivity to environmental performance degradation
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Example of Wkshop Deliverable for Each Technology
Summary – NEMS Switch (July 12, 2008 Wkshop)
Pros
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Subthresh slope << 60 mV/dec
Substantial power reduction –
lower Vdd & little static power
Logic functions ~ 1 delay time
Complementary devices to
replace n- and p-MOSFETS
NEM-FET dynamic Vth device
Fab process comp w/ CMOS
Low cost substrates
Radiation hard operation
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Cons
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Slow delay time < 1 ns
High oscillatory pull out time
High pull in voltage
Charge based switch w/
parasitics
NEM-FET is still a FET
NEM-FET not demonstrated
Limited scaling potential
Stiction issues
Controlled variability
Hermetic packaging required
Work in Progress --- Not for Publication
Emerging Research Memory Technology Select Mtg.
Agenda – Wednesday, April 7, 2010
9:00
9:10
9:20
9:45
10:45
12:20
Welcome and Introductions
Background & ERD Meeting Objectives
Review Process for selecting Emerging Research
Memory Technologies for Highlighting
Discuss Technologies
9:45 Ferroelectric FET Memory
10:05 Spin Transfer Torque RAM
10:25 Nanothermal: NW – PCM
Break
11:00 Nanothermal: Fuse/Antifuse Memory
11:20 Nanoionic Memory
11:40 Nanomechanical Memory
12:00 Electronic Effects Memory
Lunch
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Hutchby
Hutchby
Hutchby
Waser
Chung
Chen
Zhirnov
Akinaga
Zhirnov
Zhirnov
Work in Progress --- Not for Publication
Emerging Research Memory Technology Select Mtg.
Agenda – Wednesday, April 7, 2010
12:20
1:20
2:00
2:20
Lunch
Discuss Technologies
1:20 Macromolecular (polymer) Memory
Garner
1:40 Molecular Memory
Garner
Memory Devices: Energy-Space-Time Tradeoffs
Cavin
Execute Memory Technology Selection Process
2:20
Preliminary vote on technologies – Majority voting process
2:30
Discuss preliminary results
2:50
Second vote on technologies
3:00
Discuss the leading technologies resulting from vote
3:40
Final vote on the 4 – 5 leading technology(ies) to
determine if we have approximate consensus (75% of
those voting) to recommend one or more for roadmapping
and accelerated development
3:50 Decide next steps in roadmapping the chosen
technology(ies)
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Emerging Research Memory Technology Select Mtg.
Agenda – Wednesday, April 7, 2010 (cont’d)
4:10
Break
4:30
Regular ERD Business Meeting
4:30 ERD Architecture Workshop (August xxx)
Cavin
4:45 ERD Device Workshop (Sept. 17)
Hutchby
5:00 ERD Analog & RF Workshop (Nov. 30)
Brillouet
5:15 ERM Mat’ls for Accelerated Memory (Nov.30)
Awano
5:30 Review of ERM Workshops
Garner
5:45 Adjourn
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Process Proposed for Selecting an Emerging Research
Memory Technology for Accelerated Development
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Receive and evaluate White Papers from Proponents
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Conduct an ERD Telecon to briefly review and discuss the White
Papers to provide feedback prior to Workshop.
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Agree on major technical criteria for each new memory technology
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Agree on voting criteria
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Receive proponent/opponent expert inputs on the candidate
technologies on Tuesday, April 6.
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Select any candidate technologies meriting accelerated development
via discussion, majority voting, and forming an approximate
consensus on Wednesday, April 7.
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Report results to IRC on April 8 or 9.
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Write a report by May 31.
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Decision Making & Majority Voting Scheme
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Each member of ERD WG will be given a maximum of 4 votes
to use in voting for their top 4 choices among the candidate
technologies (Majority Voting scheme)
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Only 0 or 1 vote can be cast for any candidate technology
Member does not have to use all 4 votes, but cannot use more
than 4 votes.
ERD/ERM WG members and other individuals present in the April
6th Workshop & the April 7th FxF meeting will be eligible to
participate in the votes in the April 7th meeting, based on their
personal technical judgment, independent of their corporate
affiliation or regional representation.
The Candidate Technologies will be ordered according to
which received the largest number of votes.
Consensus approval will be our goal, but a 75% affirmative
vote is desired as a minimum. This is what is meant by the
term approximate consensus.
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ERD/ERM Business Meeting
April 7, 2010
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2010 ERD Working Group Organization
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ERD Function
Chapter Chair – North America
Chapter Co-chair – Europe
Chapter Co-chair – Japan ERD
Chapter Co-chair – Korea ERD
Memory
Logic
Architecture
Editorial Team
ITRS Liaisons
– PIDS
– FEP
– Modeling & Simulation
– Materials
– Metrology
– Design
– More than Moore
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Leader
Hutchby
Ionescu
Hiramoto
Chung
Zhirnov
Bourianoff
Cavin
Hutchby, Bourianoff, Cavin,
Chung, Garner/Herr, Hiramoto,
Ionescu, Zhirnov
Ng, Hutchby
Colombo
Shankar/Das
Garner
Herr
Yeh/Bourianoff
Brillouet
Work in Progress --- Not for Publication
2010 ERD Update Schedule
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April 6-7
– Memory Workshop
April 7
– ERD Business Meeting
April 8 – 9 – ITRS Meetings (no public conference)
June 30?
– ERD Presentation draft for July 14 Conf due to Linda Wilson
August xx
– Architecture Workshop
July 11
– ERD Business Meeting
July 12 – 13 – ITRS Meetings
July 14
– ITRS Public Conference
Sept. 17
– Logic Device Workshop
Sept. 17
– ERD Business Meeting
August ?
– ERD Chapter Update Material Due*
Sept. ?
– 2008 ITRS Update Content Frozen*
Nov. 30
– 2011 ERD Chapter Kickoff Meeting in Tsukuba, Japan
Dec. 1 – 2
– ITRS Meeting in Tsukuba, Japan
Dec. 3
– ITRS Public Conference in Makuhari Messe, Japan
Dec, 5
– 2011 ERD Chapter Kickoff Meeting in San Francisco @IEDM
* ERD typically uses the “update year” to prepare for the following “chapter
re-write year (i.e. 2011)” and does not provide an update.
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ERD FxF Workshops for 2010
Workshop topic
Date
Location
Meeting
Specific technology entries
Performance analysis for various types of Emerging research
memories including:
Emerging Research Memory
April 6-7
Devices
2010
Varese, Italy
ITRS Spring
meeting
- Spin Transfer Torque MRAM
- Nanoionic Memory (e.g. the memrister)
-Nanothermal Memory (Nanowire Phase-Change Memory)
- Electronics Effects Memory
- Molecular Memory
- Performance analysis/benchmarking of various Emerging
research
Emerging Research
July 11
Architectures
2010
Semicon West
information
processing
device
technologies
including:
- pseudospintronic (e.g., the BiSFET)
- Spin devices
- Spin wave devices
Emerging Research Logic
Sept. 17
Devices
2010
1.
ESSDERC
- Optimum circuit architectures associated with novel devices
RF and Analog Properties
of Emerging Research
Devices
2.
Seville, Spain
- Nonlinear response functions
- Devices for “functional diversification”?
Materials for Select
Nov. 30
2010
Tokyo, Japan
Winter ITRS
To be Determined
Mtg
Memories
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Action Items (1/2)
1.
2.
3.
4.
5.
6.
7.
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Action Items (2/2)
8.
9.
10.
11.
12.
13.
14.
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