Transcript Document

TPU: time functions
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Input event detection
Output event generation
Pulse-rate sensing
Pulse-rate modulation
Pulse-width modulation
Time Processor Unit (TPU)
TPU
TPU
Serial
Comm
ADC
ADC
IMB
U-bus
RCPU
SRAM
SRAM
L-bus
U-bus
System
Interface
Unit
(USIU)
TPU
Controls 16 channels (available as pins).
Can observe events on these channels (input).
Can generate events on these channels (output).
Events: transitions to indicate some state.
TPU
Memory-mapped
interface
16-bit
counters
TCR1
IMB3
System
Config.
TCR2
Channel
control
MicroEngine
Parameter
RAM
channels
Chan 0
Chan 1
Chan 15
TPU Timers
Two timers: TCR1 & TCR2 -- 16 bits each
All channel events are created or captured
w.r.t. a timer.
TCR1 programmed in TPUMCR.
TCR2 can be driven by an external clock.
TPU Registers
TPU Module Configuration Register: TPUMCR
0x30 4000
0
1:2
TCR1P
00: div by 1
01: div by 2
10: div by 4
11: div by 8
8
9
supvpsck
Clock prescalar
0: 32
1: 4
TPU Control Registers
TPU Interrupt Configuration Register (TICR)
0x30 4008
0:4
5:7
8:9
CIRL
Channel interrupt
request level: 0-7.
ILBS
TPU Control Registers
Channel Interrupt Enable Register (CIER)
0x30 400a
0
1
2
Ch
15
Ch
14
Ch
13
0: interrupt disabled
1: interrupt enabled
14
Ch
1
15
Ch
0
TPU Control Registers
Channel Interrupt Status Register (CISR)
0x30 4020
0
1
2
Ch
15
Ch
14
Ch
13
14
Ch
1
Channel interrupt status:
0: interrupt not asserted
1: interrupt asserted
15
Ch
0
Channel Programming
16 predefined functions.
Input Capture: capture one or multiple
transitions on an input pin.
Channel 0
Capture the time of the transition
Channel Programming
Program as an output channel.
Output Compare: generate an event on the
output: a single output transition, a single
pulse, or a continuous 50% duty cycle pulse
train.
REF_TIME1
offset
Ref_Time = REF_TIME1 + offset
Channel Initialization
Choose channel function: Code for IC: 0xA
Channel function code for OC: 0x4
0x30 400c: Channel Function Select Register 0 (CFSR0)
Ch 15
Ch 14
Ch 13
Ch 12
0x30 400e: Channel Function Select Register 1 (CFSR1)
Ch 11
Ch 10
Ch 9
Ch 8
0x30 4010: Channel Function Select Register 2 (CFSR2)
Ch 7
Ch 6
Ch 5
Ch 4
0x30 4012: Channel Function Select Register 3 (CFSR3)
Ch 3
Ch 2
Ch 1
Ch 0
Input Capture Parameters
Channel W
0x3041W0
Channel Control (9 bits)
0x3041W2
0x3041W4
MAX_COUNT
0x3041W6
TRANS_COUNT
0x3041W8
FINAL_TRANS_TIME
0x3041Wa
LAST_TRANS_TIME
Input Capture/Transition Counter
Input Parameters:
MAX_COUNT:
The TPU raises an interrupt after counting as
many events as MAX_COUNT.
Output Parameters:
TRANS_COUNT: current count of captured
transitions.
FINAL_TRANS_TIME: Timer time when the final
transition (MAX_COUNTth) is captured.
LAST_TRANS_TIME: Timer time when the last
transition (TRANS_COUNTth) is captured.
Memory Map of Parameters
Channel 0:
MAX_COUNT: 0x30 4104
TRANS_COUNT: 0x30 4106
FINAL_TRANS_TIME: 0x30 4108
LAST_TRANS_TIME: 0x30 410A
General Channel Y:
MAX_COUNT: 0x30 41Y4
TRANS_COUNT: 0x30 41Y6
FINAL_TRANS_TIME: 0x30 41Y8
LAST_TRANS_TIME: 0x30 41YA
General Parameter Memory Map
0x3041
00
Ch 0
P1
10
Ch 1
P1
20
Ch 2
P1
f0
Ch 15
P1
02
04
06
08
0a
0c
0e
P2
P3
P4
P5
P6
P7
P8
12
14
16
08
1a
1c
1e
P2
P3
P4
P5
P6
P7
P8
22
24
26
28
2a
2c
2e
P2
P3
P4
P5
P6
P7
P8
f2
f4
f6
f8
fa
fc
fe
P2
P3
P4
P5
P6
P7
P8
Channel Control Options
Part of channel initialization
0:6
7:10
11:13
TBS
Time Base Selection
00xx: input channel
000x: capture TCR1
001x: capture TCR2
PAC
14:15
PSC
Pin State Control
11:do not force any state
input pin
01: force high
10: force low
Pin Action Control
000:do not detect trans.
001:detect rising edge
010:detect falling edge
011:detect either edge
1xx:do not change PAC
Channel Priority
Choose channel priority: 0:disable; 1:low;
2: medium; 3: high
0x30 401c: Channel Priority Register 0 (CPR0)
Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10
Ch 9
Ch 8
0x30 401e: Channel Priority Register 1 (CPR1)
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Channel Function Activation
After initializing channel, the channel function
is activated by host service request, which can
be further specialized through host sequence.
0x30 4018: Host Service Request Register 0 (HSRR0)
Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10
Ch 9
Ch 8
0x30 401a: Host Service Request Register 1 (HSRR1)
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Host Sequence
0x30 4014: Host Sequence Register 0 (HSQR0)
Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10
Ch 9
Ch 8
0x30 4016: Host Sequence Register 1 (HSQR1)
Ch 7
Ch 6
Ch 5
Ch 4
Transition sequencing:
x0: single shot
x1: continual
Ch 3
Ch 2
Ch 1
Ch 0
Typical Initialization Sequence
• Disable the channel before programming it
– CPR[ch]  00 (channel priority – disabled)
• Assign the channel function
– CFSR[ch]  0xA (for input capture/ITC)
• Program the function parameters
– MAX_COUNT=1 for input capture
– Channel control: TBS: 000x (input channel; capture TCR1); PAC: 001
(detect rising edge); PSC: 11 (do not force)
– Host sequence single shot. Write 00 into HSQRR[ch].
– etc.
• Initialize host service (activate the channel):
– HSRR[ch]  01 (initialize TCR mode)
• Enable the channel:
– CPR[ch]  01, 10, 11
Shared Register Modification
0x30 401a: Host Service Request Register 1 (HSRR1)
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
00: Host service complete  by TPU channel
01: Initialize TCR mode  by CPU Program
Modification of HSRR involves read-modify-write:
lhz r6, 0x401a(r5) //read
andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0])
ori r6, r6, 0x1
sh r6, 0x401a(r5) // write
Does it work?
How many independent potential writers into HSRR1?
Shared Register Modification Contd.
lhz r6, 0x401a(r5) //read
00
00
10
00
00
11
01
00
andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0])
ori r6, r6, 0x1
00
00
10
00
00
11
01
01
00
00
10
00
00
11
00
00
sth r6, 0x401a(r5) // write
We don’t really know what happens to ch 1-7 fields
while we modify ch 0 field.
Shared Register Modification Contd.
Solution: into ch 1-7 fields, write something we
are definitely not supposed to write.
00 is written by only the TPU, no CPU program
should legitimately write that value.
li r6, 0x1 //00 00 00 00 00 00 01
sth r6, 0x401a(r5)
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
00
00
10
00
00
11
00
00
01
Write guard logic only allows 01, 10, 11 to go through!
Output Compare (OC)
REF_TIME1
offset
Ref_Time = REF_TIME1 + offset
The pin state is not forced into an immediate output.
REF_TIME1
offset
Ref_Time = REF_TIME1
+ offset
Pin state forced to high (immediate output selected).
Output Compare (OC)
OC parameters specified by the CPU program:
REF_TIME1 as a pointer into the parameter space
of any of the 16 channels.
Parameter address space: 0x3041 00 – 0x3041 fe
Need to specify only 8-bits of address for
REF_ADDR1.
OFFSET: a 16-bit quantity: 0x0 – 0x8000.
OC Programming
(REF_ADDR1)
OFFSET
REF_TIME = (REF_ADDR1) + OFFSET
Point REF_ADDR1 to 0x3041 ec (TCR1 value captured
at this parameter address).
OFFSET = 0x1000
with TCR1 resolution at 1 micro-s: 4.096 milli-s.
Channel function code for OC: 0x4
CFSR[ch]  0x4
Output Compare
OC initialization (host service request of 01
-- host initiated pulse mode) writes the
current value:
TCR1  0x3041 ec; TCR2  0x3041ee
(REF_ADDR1)
OFFSET
REF_TIME = (REF_ADDR1) + OFFSET
Program channel 0 for this pulse.
OC Channel Control Options
0:6
7:10
11:13
TBS
Time Base Selection
01xx: output channel
0100: capture TCR1, match TCR1
0101: capture TCR1, match TCR2
0110: capture TCR2, match TCR1
0111: capture TCR2, match TCR2
1xxx: do not change TBS
14:15
PAC
PSC
Pin State Control
11: do not force any state
01: force high
10: force low
Pin Action Control
000: do not change pin state on match
001: high on match
010: low on match
011: toggle on match
1xx: do not change PAC
OC Channel Control
(REF_ADDR1)
OFFSET
REF_TIME = (REF_ADDR1) + OFFSET
Capture TCR1, match TCR1
0100
Do not force initial state
011
Toggle on match
11
OC Channel Control
(REF_ADDR1)
OFFSET
REF_TIME = (REF_ADDR1) + OFFSET
Capture TCR1, match TCR1
0100
Force high
010
Low on match
01
Other OC Parameters
Channel W
0x3041W0
Channel Control (9 bits)
0x3041W2
OFFSET
0x3041W4
RATIO
0x3041W6
REF_ADDR2
0
REF_ADDR1
0
REF_ADDR3
0
0x3041W8
REF_TIME
0x3041Wa
ACTUAL_MATCH_TIME
We will write 0’s into RATIO, REF_ADDR2, and
REF_ADDR3.
OC Output Parameters
When a channel is initialized for OC through a
service request of 01, REF_TIME is computed
as (REF_ADDR1) + OFFSET and placed in
parameter REF_TIME.
REF_TIME is the next time instant when an
event would occur (and an interrupt is raised).
This is the match event: compare TCR1/2
with REF_TIME for a match.
ACTUAL_MATCH_TIME is updated with the TCR1/2
time when the match is serviced (by raising an
interrupt, and changing the level of the output
channel).