Transcript Subsystems 3

Topics
•
Memories:
–
–
–
–
•
•
•
ROM;
SRAM;
DRAM;
Flash.
Image sensors.
FPGAs.
PLAs.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
High-density memory
architecture
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Copyright  2008 Wayne Wolf
Memory operation
•
Address is divided into row, column.
– Row may contain full word or more than one
word.
•
•
Selected row drives/senses bit lines in
columns.
Amplifiers/drivers read/write bit lines.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Read-only memory (ROM)
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•
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ROM core is organized as NOR gates—
pulldown transistors of NOR determine
programming.
Erasable ROMs require special processing
that is not typically available.
ROMs on digital ICs are generally maskprogrammed—placement of pulldowns
determines ROM contents.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
ROM core circuit
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Static RAM (SRAM)
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•
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Core cell uses six-transistor circuit to store
value.
Value is stored symmetrically—both true
and complement are stored on crosscoupled transistors.
SRAM retains value as long as power is
applied to circuit.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
SRAM core cell
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
SRAM core operation
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Read:
– precharge bit and bit’ high;
– set select line high from row decoder;
– one bit line will be pulled down.
•
Write:
– set bit/bit’ to desired (complementary) values;
– set select line high;
– drive on bit lines will flip state if necessary.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
SRAM sense amp
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Copyright  2008 Wayne Wolf
Sense amp operation
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•
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Differential pair—takes advantage of
complementarity of bit lines.
When one bit line goes low, that arm of diff
pair reduces its current, causing
compensating increase in current in other
arm.
Sense amp can be cross-coupled to increase
speed.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
3-transistor dynamic RAM
(DRAM)
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First form of DRAM—modern commercial
DRAMs use one-transistor cell.
3-transistor cell can easily be made with a
digital process.
Dynamic RAM loses value due to charge
leakage—must be refreshed.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
3-T DRAM core cell
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3-T DRAM operation
•
•
Value is stored on gate capacitance of t1.
Read:
– read = 1, write = 0, read_data’ is precharged;
– t1 will pull down read_data’ if 1 is stored.
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Write:
– read = 0, write = 1, write_data = value;
– guard transistor writes value onto gate
capacitance.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
3-T DRAM operation
•
•
Value is stored on gate capacitance of t1.
Read:
– read = 1, write = 0, read_data’ is precharged;
– t1 will pull down read_data’ if 1 is stored.
•
Write:
– read = 0, write = 1, write_data = value;
– guard transistor writes value onto gate
capacitance.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
1-T DRAM
•
•
•
Word line controls
pass transistor.
Pass transistor guards
access to capacitor.
Read is destructive.
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Stacked capacitor DRAM
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Trench capacitor DRAM
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Floating gate transistor
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Poly 1 gate is not
connected.
Schematic symbol:
poly 2
SiO2
poly 1
n+
n+
p
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Copyright  2008 Wayne Wolf
Fowler-Nordheim tunneling
+
20 V
poly 2
floating
p+
n+
poly 1
-
n+
SiO2
-
n+
p
n-well
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Copyright  2008 Wayne Wolf
Fowler-Nordheim erasing
20 V +
floating
p+
n+
n+
poly 2
SiO2
-poly -1
floating
n+
p
n-well
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Copyright  2008 Wayne Wolf
NOR flash architecture
•
Same as NOR ROM
but with floating gate
pulldowns.
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+
pullup
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NAND flash architecture
•
•
•
Want to provide
data
banked memory for
higher data
data 1 data 2
bank bank bank
throughput.
0
1
2
Widely used for data
storage.
address 21
address
Likely to become
standard architecture.
Modern VLSI Design 4e: Chapter 6
bank
3
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2-bit NAND flash cell
bit
Select top
RA0
RA1
Select bottom
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n+ source
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NAND flash cell programming
+20V
Select top
+20V
RA0
bit
+7V
Row not
programmed
+5V
RA1
0V
Select bottom
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Wear in flash memory
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•
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Write cycles slowly damage devices.
Limited number of write cycles: 10,000.
Software balances utilization of locations to
level wear across the device.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Image sensors
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Two major types of image sensors:
– Charge-coupled device (CCD) requires
specialized fabrication steps.
– CMOS image sensor uses standard CMOS
technology, perhaps with low-noise
modifications.
•
CMOS image sensor is an array circuit
similar to a RAM.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Photodiodes
•
•
Photodiode turns
photons into electrons.
Photocurrent density:
x1
n
x2
p
photons
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+
x3
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Active pixel sensor (APS) circuit
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APS column
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
SRAM-based FPGAs
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Program logic functions, interconnect using
SRAM.
Advantages:
– dynamically reconfigurable;
– uses standard processes.
•
Disadvantages:
– SRAM burns power.
– Possible to steal, disrupt configuration bits.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Logic elements
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•
Logic element includes combinational
function + register(s).
Use SRAM as lookup table for
combinational function.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
LUT-based logic element
inputs
Lookup
table
configuration
bits
out
Can multiplex at output or address at input
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Example
111
1, 1, 1, 0,
0,
1, 1, 0,
1, 0,
1, 10
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0 1
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Evaluation of SRAM-based LUT
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N-input LUT can handle function of 2n
inputs.
All logic functions take the same amount of
space.
SRAM is larger than static gate equivalent
of function.
Burns power at idle.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Static CMOS gate vs. LUT
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Number of transistors:
– NAND/NOR gate has 2n transistors.
– 4-input LUT has 128 transistors in SRAM, 96 in
multiplexer.
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Delay:
– 4-input NAND gate has 9t delay.
– SRAM decoding has 21t delay.
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Power:
– Static gate’s power depends on activity.
SRAM
burns power.
Modern VLSI–
Design
4e: Chapter always
6
Copyright  2008 Wayne Wolf
Registers in logic elements
•
Want to selectively add register to LE:
Configuration bit
Comb
logic
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LE out
D
Q
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Other LE features
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•
Multiple logic functions in an LE.
Addition logic:
– carry chain.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Programmable interconnect
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MOS switch controlled by configuration bit:
D
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Q
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Programmable vs. fixed
interconnect
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Switch adds delay.
Transistor off-state is worse in advanced
technologies.
FPGA interconnect has extra length = added
capacitance.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Programmable logic array (PLA)
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Used to implement specialized logic
functions.
A PLA decodes only some addresses (input
values); a ROM decodes all addresses.
PLA not as common in CMOS as in nMOS,
but is used for some logic functions.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
PLA organization
p1
p2
AND plane
p3
OR plane
p4
i0 i0’
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i1 i1’
product term
f0
f1
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PLA structure
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AND plane, OR plane, inverters together
form complete two-level logic functions.
Both AND and OR planes are implemented
as NOR circuits.
Pulldown transistors form
programming/personality of PLA.
Transistors may be referred to as
programming tabs.
Modern VLSI Design 4e: Chapter 6
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PLA AND/OR cell
input 1
input 2
programming
tab
output 1
output 2
no tab
VSS
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf