Transcript Figure 9.01
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Main Memory
CISC3595, Fall 09
Memory Management
Background Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium 2
Background
Main memory and registers are only storage CPU can access directly Register access: one CPU clock (or less) Main memory access: many CPU cycles Cache sits between main memory and CPU registers Memory is cheap today, and getting cheaper But applications are demanding more and more memory, there is never enough! 3
Review: Logic View of a Computer
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Main memory:
a large array of words or bytes. Each words has its own address.
Review: Main (Primary) Memory
Main memory – the only large storage media that CPU can access directly Capacity: Bandwidth Peak: one word per bus cycle CPU access main memory directly through local bus, i.e., system bus 5
Review: Performance of different storage
< 16 GB ns: nanosecond (10 -9 seconds), 1 billionth second 6
Program execution
Program must be brought (from disk) into memory and placed within a process for it to be run A program: a sequence of instructions stored in memory (main memory or disk) Multiprogramming: multiple processes are loaded into memory to run simultaneously Increase CPU utilization Swapping: a process might be temporarily swapped to disk, and reloaded back into memory 7
The need for memory management
Memory Management, involves swapping blocks of data from secondary storage Bring processes into main memory for execution by processor Protection of memory required to ensure correct operation
Memory needs to be allocated to ensure a reasonable supply of ready processes to consume available processor time
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Memory Management Requirements
Relocation Protection Sharing Logical organisation Physical organisation 9
Requirements: Relocation
Programmer does not know where the program will be placed in memory when it is executed it may be swapped to disk and return to main memory at a different location (relocated) Memory references in the program must be translated to actual physical memory address 10
Multistep Processing of a User Program Programmer’s view of a program/process?
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Multistep Processing of a User Program Compiler seldom knows where an object will reside, it assumes a fixed base location (for example, zero). 12
Multistep Processing of a User Program • Linker/Linkage editor * combines multiple object files into a executable program, resolving symbols as it goes along.
arranges objects in a program's address space . Relocating code that assumes a specific base address to another base 13
Dynamic Linking
Linking postponed until execution time Small piece of code,
stub
, used to locate appropriate memory-resident library routine Stub replaces itself with the address of the routine, and executes routine Operating system needed to check if routine is in other processes’ memory address Dynamic linking is particularly useful for libraries also known as shared libraries 14
Multistep Processing of a User Program
Loader
start up programs: read executable files into memory, carry out other required preparatory tasks so that the process can run Unix loader , i.e., handler for execve() : * validation (permissions, memory requirements etc.); •Copy program image from disk into memor •Copy command-line arguments on stack • Initialize registers (e.g., stack pointer) • Jump to program entry point (_start) 15
Dynamic Loading Mechanism
Allow a program to load, execute and unload library (or binary code) at run time A program, at runtime, loads a library (or other binary) into memory retrieves addresses of functions and variables contained in the library executes those functions or access those variables unloads library from memory. Better memory-space utilization: unused routine is never loaded Useful when large amounts of code are needed to handle infrequently occurring cases 16
Dynamic Loading (cont’d)
Standard POSIX/UNIX API #include
Address Binding A program must be brought to main memory. instructions that use addresses in a program, must be bound to proper address space in main memory Address another binding : a mapping from one address space to Complier: bind symbolic (variable names) to relocatable address, i.e., 14 byte from beginning of this module Linker: bind relocatable addresse to absolute address (74014) space of a process address space 18
Final Address Binding Final address binding: the final mapping of instructions/data to physical memory address Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time: must generate relocatable code if memory location is not known at compile time Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers) 19
Logical vs. Physical Address Space
Logical address – generated by CPU; also referred to as virtual address User program deals with logical addresses; it never sees the real physical addresses Physical address – address seen by memory unit Memory-management Unit (MMU): address space hardware for run time mapping from logical address space to a physical Many different schemes for the mapping First let’s see an simple example… 20
Memory-Management Unit: an example
Value in relocation register is added to every address generated by a user process at the time it is sent to memory
Requirements: Protection
Processes should not be able to reference memory locations in another process without permission Unless special arrangement is made, e.g., shared memory segment is setup Memory protection checking performed at run time Impossible to check absolute addresses to ensure protection at compile time Program might calculate address at run time, e.g., access array element, pointer to a data structure By the processor (hardware) OS cannot anticipate all memory reference of a program Too time consuming if done by software 22
Address protection: base and limit registers 23
Requirements: Sharing
Allow several cooperating processes to access same portion of memory Allow multiple processes running same program to access same copy of the program rather than have their own separate copy 24
Requirements: Logical Organization
Programs are written in modules Modules can be written and compiled independently Different degrees of protection given to modules: read-only, readable/writable Share modules among processes OS and hardware provide support for deal with such requirement through segmentation 25
Requirements: Physical Organization
Keep track of available memory blocks, allocate and reclaim them as processes come and go… Cannot leave programmer with the responsibility to manage memory Memory available for a program plus its data may be insufficient Overlaying : program and data are organized in such a way that various modules can be assigned same region of memory, main program responsible for switching modules in and out => costly for programmer Programmer does not know how much space will be available, and where 26
Roadmap: Memory Allocation Schemes
Contiguous Allocation Paging Segmentation
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Contiguous Allocation
Main memory usually divided into two partitions: Resident operating system, usually held in low memory with interrupt vector User processes held in high memory Relocation registers used to protect user processes from each other, and from changing operating system code and data Base register contains value of smallest physical address Limit register contains range of logical addresses – each logical address must be less than the limit register MMU maps logical address dynamically 28
Contiguous Allocation (Cont.)
Multiple-partition allocation Hole – block of available memory; holes of various size are scattered throughout memory When a process arrives, it is allocated memory from a hole large enough to accommodate it Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 process 8 OS process 5 OS process 5 process 9 OS process 5 process 9 process 10 process 2 process 2 process 2 process 2 29
Dynamic Storage-Allocation Problem
How to satisfy a request of size
n
from a list of free holes First-fit: Allocate the
first
enough hole that is big Best-fit: Allocate the enough; must search entire list, unless ordered by size
smallest
hole that is big Produces the smallest leftover hole Worst-fit: Allocate the
largest
search entire list Produces the largest leftover hole hole; must also 30 First-fit and best-fit better than worst-fit in terms of speed and storage utilization
Fragmentation problem
External Fragmentation
– total memory space exists to satisfy a request, but it is not contiguous
Internal Fragmentation
– allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Reduce external fragmentation by
compaction
Shuffle memory contents to place all free memory together in one large block Possible only if relocation (final binding to memory address) is done at execution time To solve external fragmentation problem Allocate noncontiguous memory to process Paging, Segmentation, and Combined 31
Paging
Physical address space of a process can be noncontiguous process is allocated physical memory wherever it is available Logical address space of a process is still contiguous Physical memory divided into fixed-sized blocks called
frames
Frame size is power of 2, between 512 bytes and 8,192 bytes Logical memory divided into blocks of same size called
pages
System keeps track of all free frames To run a program of size
n
pages, need to find n free frames Set up a page table for logical => physical addresses translation Paging scheme address external fragmentation internal fragmentation is still possible 32
Paging Model of Logical and Physical Memory A process’s page table : for logical => physical addresses translation * contains base address of each page in physical memory 33
Logic address under Paging scheme
Logical address (address generated by CPU) is divided into: Page number (p) –an index into a page table which contains base address of each page in physical memory Page offset (d) – relative address (within page), combined with base address to define physical memory address that is sent to the memory unit page number
p m - n
page offset
d n
For given logical address space 2
m and page size 2
n 34
MMU: Paging
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Paging Example
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Free Frames
37 Before allocation After allocation
Implementation of Page Table
Where to store the page tables ?
Register? too small Page table is kept in main memory
Page-table base register (PTBR)
points to the page table
Page-table length register (PRLR)
indicates size of the page table Every data/instruction access requires two memory accesses One for page table and one for the actual data/instruction.
To avoid two memory access problem….
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Associative Memory
a special fast-lookup hardware cache called
associative
memory or translation look-aside buffers (TLBs) Some TLBs store address-space identifiers (ASIDs) in each entry – uniquely identifies each process to provide address space protection Associative memory – parallel search for all entries Page # Frame # 39 Address translation (p, d) If p is in associative register, get frame # out Otherwise get frame # from page table in memory
Paging Hardware With TLB
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Effective Access Time
Associative Lookup = time unit (e.g. 20 ns) Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers Hit ratio = (e.g. 80%) Time to access memory (e.g. 100 ns) Effective Access Time (EAT) e.g. EAT = 0.80 x 120 + 0.20 x (100+100+20) (found in TLB) (not found in TLB) =140 ns 41
Memory Protection
Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page “invalid” indicates that the page is not in the process’ logical address space 42
Valid (v) or Invalid (i) Bit In A Page Table
Most processes do not use whole logic address space Address space: 2 Page size: 2KB 14 (0, …, 16383), Process use only 0 to 10468 Alternative: page-table length register (PTLR) 43
Shared Pages
Useful for shared code (reentrant code, pure code) One copy of read-only code shared among processes (i.e., text editors, compilers, window systems).
Each process has its own copy of registers and data storage to hold its data Shared code page and private data page 44
Shared Pages Example
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Structure of the Page Table
To support large logic address space up to 2 32 or 2 64 page table too large to put in a contiguous memory Solutions Hierarchical Paging Hashed Page Tables Inverted Page Tables 46
Hierarchical Page Tables
Break up the logical address space into multiple page tables A simple technique is a two-level page table e.g. for large logical address spaces 2 32 to 2 64 47
Two-Level Page-Table Scheme
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Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into: a page number consisting of 22 bits a page offset consisting of 10 bits Since the page table is paged, the page number is further divided into: a 12-bit page number a 10-bit page offset Thus, a logical address is as follows: page number
p
i
p
2 12 10 page offset
d
10 49 where p
i
is an index into the outer page table, and p
2
within the page of the outer page table is the displacement
Address-Translation Scheme
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Three-level Paging Scheme
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Hashed Page Tables
Common in address spaces > 32 bits Virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.
Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.
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Hashed Page Table
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Inverted Page Table
One entry for each real page of memory Entry consists of virtual address of the page stored in that real memory location, with information about process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one — or at most a few — page-table entries 54
Inverted Page Table Architecture
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Segmentation
Memory-management scheme that supports user view of memory A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays 56
Logical View of Segmentation
1 4 1 2 3 4 2 3 user space physical memory space 57
Segmentation Architecture
A process’s logical address consists of a two-tuple:
Segment-table base register (STBR)
points to segment table’s location in memory
Segment-table length register (STLR)
indicates number of segments used by a program segment number
s
is legal if
s
<
STLR
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Segmentation Architecture (Cont.)
Protection With each entry in segment table associate: validation bit = 0 illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level Since segments vary in length, memory allocation is a dynamic storage-allocation problem 59
Segmentation Hardware
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Example of Segmentation
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Example: The Intel Pentium
Supports both segmentation, and segmentation with paging CPU generates logical address Given to segmentation unit Which produces linear addresses Linear address given to paging unit Which generates physical address in main memory 62
Logical => Physical Address: in Pentium 63
Intel Pentium Segmentation
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Pentium Paging Architecture
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Linux on Pentium Systems
Uses six segments: 1. A segment for kernel code 2. A segment for kernel data 3. A segment for user code 4. A segment for user data 5. A task-state segment (TSS) 6. A default local descriptor table (LDT) segment 66
Three-level Paging in Linux
Linear Address in Linux
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