Transcript Engineering Brief ENGR 101 - Coastal Carolina University

Integrating
Field Programmable Gate Arrays
Across a Traditional Computer Science Curriculum
Dr. William M. Jones
Computer Science Department
Coastal Carolina University
Computer Security Conference 2009
Partial Curricular Track
Assembly Programming
Compiler Design
Digital Logic
Computer Architecture
Digital Security?
Design an ISA
Implement the CPU
Write a Compiler
Assembler
Assembly
Programming
Common
Target
Computing
Platform???
Digital Logic
Architecture
Compiler
Design &
Implementation
ASICs
IC’s
Over-simplified
Diagram
General
Purpose
Machines
FPGAs
A Simple Multiplexer
(Digital Logic)
MUX Implementation with Pure Logic
Synthesized Hardware (Pure Logic)
But what do you do now?
MUX Implementation with WHEN/ELSE
Synthesized Hardware (WHEN/ELSE)
A Simple ALU (Digital Logic/Comp. Arch.)
ALU Specifications
ALU Part 1
ALU Part 2
ALU Part 3
Assembly Programming
Machine Code
Assembly Code
Potential Layout

Digital Logic
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Assembly Programming
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Give students a working CPU
Give students an assembler
Have them write programs, and load into FPGA
Computer Architecture
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
Schematic Capture, Truth Tables, VHDL
Conceive of an ISA
Implement CPU (or modify base structure)
Compilers
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Give the students an ISA
Have them write compiler and assembler to match ISA
Load output into FPGA and see what happens
Design an ISA
Implement the CPU
Complete the Cycle w/
An FPGA
Write a Compiler
Assembler
So What Do You Need?

An FPGA Development Board/Kit
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IDE
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Xilinx
Altera
$150 - $500 ($275 each)
ISE
Quartus
University programs / freely available
Host Computer
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PC
Laptop
USB
Digital Signal Processing, Video,
Networking, Embedded Systems
What about computer security?
Prototyping
Low Cost
Deployed in Various Products
Hardware Security

Black Box Attacks
–
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Readback Attacks
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Configuration stored in SRAM
Reverse-Engineering Bitstreams
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Debugging backdoors, fault injection
Clone SRAM
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Input data, listen for return, infer inner workings
Security through obsecurity
Physical Attacks
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I/O pin probing
Thank you!
Questions?
http://www.parl.clemson.edu/~wjones
Demo Available
OUTPUT
LEDR[17]
AND2
INPUT
VCC
INPUT
VCC
SW[0]
PIN_N25
PIN_N26
SW[1]
PIN_AD12
OR2
inst
OUTPUT
LEDG[0]
PIN_AE22
inst2
AND2
INPUT
VCC
INPUT
VCC
SW[2]
SW[3]
OUTPUT
LEDR[16]
PIN_AE12
inst1
bit_3_count
up counter
clock
q[2..0]
q[2..0]
OUTPUT
q[3]
LEDG[6]
PIN_U17
LEDG[7]
OUTPUT
q[1]
inst3
q[0]
PIN_G26
INPUT
VCC
OUTPUT
KEY [0]
LEDG[5]
PIN_P25
PIN_AE14
PIN_AA20
PIN_Y18