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‫ מכון טכנולוגי לישראל‬- ‫הטכניון‬
‫הפקולטה להנדסת חשמל‬
Technion - Israel institute of technology
department of Electrical Engineering
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
)’‫דו”ח סיכום פרויקט (חלק א‬
Subject:
Project name
Performed by: Daniel Heifetz, Vladimir
Lifliand
Instructor: Dimitry Sokolik
2001/2002 ‫סמסטר (חורף) שנה‬
1
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Abstract
The purpose of the system is to transfer
the picture produced by the Kirilian
camera to the PC for image processing
and research. This is done using a CCD
sensor and interface circuitry. The system
is connected to the PC using the very
popular and widely used USB interface.
2
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
System description
Main components of the system: 800x600 CCD sensor, FIFOs
which receive the image from the CCD, USB bus controller for
PC interfacing and ALTERA FPGA to control all of the above.
When a command is received from the PC software through the
USB bus, CCD takes a picture which is stored immediately in the
FIFO’s. Then the picture is transferred to the PC using the USB
controller and can stored or displayed. The transfer speed is
limited by the USB bus throughput which is 12Mbit/sec max.
The ALTERA component leads the process decoding the
commands sent from the PC, controlling the CCD sensor the
FIFOs and the USB controller.
3
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Specification
• OmniVison 800x600 CCD sensor, OKI 2x 1Mbit FIFO,
Flex 10K50 Altera, ScanLogic SL811S USB slave controller.
• Windows client application, written using MFC.
4
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
System Block Diagram
USB Controller
(slave)
USB Bus
Personal Computer
Control
Data
Control
USB Control Unit
(FPGA)
Control
Data
Camera Control Unit
(FPGA)
Control
USB Request Decoder
(FPGA)
Control
Control
Sensor
Change Camera
Registers (SCCB bus)
(FPGA)
FIFO Reset
FIFO Read Control
Control
Control
via SCCB bus
Data
Control
Control
FIFO
Control
Unit
(FPGA)
FIFO Write Control
Implemented
in Altera
FIFO 1
FIFO 2
5
Data
Control
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
FPGA Block Diagram
To SL811S chip
From FIFO
Data[7..0]
SL811S init
module
SL811S I/O
module
SL811S
Interrupt
decoder
Function EP0
(setup/control)
Internal bus and inter-block controls
Function EP1
(Read)
Function EP2
(Write)
Command[7..0] Data[7..0]
To FIFO
FIFO control
Camera control unit
USB resuest decode
To Sensor
SCCB bus
FIFO control unit
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