Transcript CSC205 Lecture 1

CSC205
Jeffrey N. Denenberg
Lecture #1
Introduction, Logic Circuits
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Administrative
• Handouts
– Course Syllabus (readings due before lecture)
– Lab Report Format
– Lab Assignment #1 (due next Tuesday 09/17)
• Grading
– 40% labs; do prelabs on-time and do a good job on
documentation (use a logic simulator to aid in
documentation).
– 2 midterms (30%) + final (30%)
– all labs and exams required; no incompletes make
arrangements in advance if you have a conflict.
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Number Systems
• Radix 10 – Why? (0, 1, … 9)
5,273 = 5*103 + 2*102 + 7*101 + 3*100
• Binary – Radix 2 (0,1)
– On/off
– 153 = 27 + 23 + 20 = 10001001
• Octal – Radix 8 (0, 1, … 7)
153 = 2* 82 + 3*81 + 80 = 231
• Hexadecimal – Radix 16 (0, 1, … 9, A, … F)
153 = 9*161 + 9*160 = 99
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Complements
(Representing Negative Numbers)
• Signed-magnitude Binary
9 = 00001001
Sign bit
-9 = 10001001
-1
0
000
1
101
-2
2
-3
3
001
101
111
010
011
• 1’s complement (complement all bits)
-9 = 11110110
• 2’s complement (add 1 to the 1’s complement)
-9 = 11110111
000
111
001
110
010
101
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100
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Other Codes
• BCD (10 4-bit binary codes per digit)
• Gray Code
only one bit changes between adjacent Digits
000
100
001
101
011
111
010
110
• ASCII – table 1-7
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Digital Logic
• Binary system -- 0 & 1, LOW & HIGH, negated
and asserted.
• Basic building blocks -- AND, OR, NOT
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Digital Logic Continued
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Many representations of digital logic
• Transistor-level
circuit diagrams
• Gate symbols (for simple elements)
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• Truth tables
• Logic diagrams
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• Prepackaged building blocks, e.g. multiplexer
• Equations: Z = S A + S  B
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• Various hardware
description
languages
– ABEL
– VHDL
• We’ll start with
gates and work
our way up
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Logic levels
• Undefined region
is inherent
– digital, not analog
– amplification,
weak => strong
• Switching threshold varies with voltage, temp,
process, phase of the moon
– need “noise margin”
• The more you push the technology, the more
“analog” it becomes.
• Logic voltage levels decreasing with process
– 5 -> 3.3 -> 2.5 -> 1.8 V
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MOS Transistors
Voltage-controlled resistance
PMOS
NMOS
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CMOS Inverter
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Switch model
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Alternate transistor symbols
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CMOS Gate Characteristics
• No DC current flow into MOS gate terminal
– However gate has capacitance ==> current
required for switching (CV2f power)
• No current in output structure,
except during switching
– Both transistors partially on
– Power consumption related
to frequency
– Slow input-signal rise times
==> more power
• Symmetric output structure
==> equally strong drive in
LOW and HIGH states
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