Transcript Transmission gate latches
D Clk S (a) Q D Clk S (b) Q D Clk (c) S Q Transmission gate latches
Clk D Clk Clk 1 S M Clk 1 Q M Clk 1 S S Clk MSL with unprotected input (Gerosa et al. 1994), Copyright © 1994 IEEE Q
Clk D Clk 1 Clk 1 Clk Clk 1 S M Q M Clk 1 S S removed Clk MSL with input gate isolation (Markovic et al. 2001), Copyright © 2001 IEEE Q Q
1 3 5
V DD
4 Distant driver
D
2
S
2
V SS D
1 noise on input 1 2 leakage 3 4 -particle and cosmic rays unrelated signal coupling 5 pow er supply ripple
Q Sources of noise affecting the latch state node (Partovi in Chandrakasan et al. 2001), Copyright © 2001 IEEE
D Clk Clk Q D Clk Clk Q (a)
removed
(b) Dynamic latches with gate isolation: (a) transmission gate, (b) C 2 MOS
D Clk 1 Clk Q M Clk Clk 1 Clk Clk 1 Clk Clk Clk 1 Clk Clk C 2 MOS latch (C 2 MOS) (Suzuki et al. 1973), Copyright © 1973 IEEE 1 Q
(a) (b) Comparison of MSLs: (a) timing, (b) energy
Clk D S Clk 1 Hybrid-latch flip-flip (Partovi et al. 1996), Copyright © 1996 IEEE Q
Clk D Clk I S Clk Clk 1 Semidynamic flip-flop (Klass 1998), Copyright © 1998 IEEE Q
Illustration of SDFF output glitch
S R D Clk D Q Q Sense-amplifier-based flip-flop (Montanaro et al. 1996), Copyright © 1996 IEEE
S R S R S R S R S R S R S R S R R S S R R S R S S R Q Q Q Q Q Q (a) (b) (c) S-R Latch modifications: (a) all-n-MOS push-pull (Gieseke et al. 1991); (b) complementary push-pull (Oklobdzija and Stojanovic 2001); (c) complementary push-pull with gated keeper (Nikolic et al. 1999).
R S
D Clk S S R R D Q Q Modified sense-amplifier-based flip-flop (Nikolic et al. 1999), Copyright © 1999 IEEE
Min D-Q Delay Comparison 5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
MSL C2MOS HLF F SDF F SAFF M-SAFF
CSE delay comparison (0.18
m
m, high load)
Energy breakdown (50% activity) 120 100 80 60 40 20 0 MSL C2MOS HLF F SDF F
Ext. clock Ext. data Int. clock Internal non-clk
SAFF M-SAFF
CSE energy breakdown (0.18
m
m, high load)
(a) (b) Flip-flop Comparisons: (a) delay, (b) internal race immunity (0.25
m
m, light load)
CSE energy-per-transition (0.25
m
m, light load) (Markovic et al. 2001), Copyright © 2001 IEEE
D Clk D Clk Clk 1 S M comp Clk Clk 1 Q M Clk 1 S S Clk
0.5 * 0.5
0.5
0.5 *
Q S D comp
0.5
0.5
Q S S S Q Q Gated MSL (Markovic et al. 2001), Copyright © 2001 IEEE
(a) Gated vs. conventional TG MSL: (a) timing, (b) energy (b)
D Clk CP Q
M
CP CP CP
Pulse Generator
CPI CP
Clock Control
CP P
1
Data-Transition Look-Ahead
CP CP
Data-transition look-ahead latch (Nogawa and Ohtomo 1998), Copyright © 1998 IEEE
Q
D Clk CP CP Q M CP CP CP CP CP CP DTLA-L without gating Q
Clk
Pulse Generator
CPI C
in
(CC)
Pulse generator
(a) (b) Energy comparison of DTLA-L and CMSL
CP D Data-Transition Look-Ahead CP CP XNOR Q CP CP Clk Pulse Generator Clock-on-demand PL (Hamada et al. 1999), Copyright © 1999 IEEE
XNOR "1 " "0 " "1 " C
int
"1" Clk Straightforward implementation with CMOS gates (energy inefficient)
Clk
XNOR
Clk inv inv "0 "
XNOR
"1"
Compound AND-NOR
Clk Clk CP Energy-efficient implementation with compound AND-NOR gate
Impact of circuit sizing on the energy efficiency of COD-PL (Markovic et al. 2001), Copyright © 2001 IEEE
S
*
S N D Clk Q S R Clk Q Q N R
*
R D Clk
1
R S Q
Conditional capture flip-flop (Kong et al. 2000), Copyright © 2000 IEEE
(a) (b) Timing parameters in latches and flip-flops with local clock gating (Markovic et al. 2001), Copyright © 2001 IEEE
(a) (b) Energy and EDP in latches and flip-flops with local clock gating (Markovic et al. 2001), Copyright © 2001 IEEE
Clk D CP D S S Clk S M Q M Clk S S Clk Clk Q
N-PL (c)
CP D N 1 d 1 N 2 S S Q D
N-MSL (a)
CP Q
N-PPL (d)
Clk CP Pulse Generator (b)-(d) Q
N-FF (b)
CP N-only clocked latches: (a) conventional TG MSL, (b) pulsed-latch, (c) conventional PL, (d) push-pull PL
1.2
1.0
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0 0 PL N-PPL N-FF N-PPL N-FF MSL N-PL
High-Vdd Low-Swing Clk
N-MSL 1 2 3 4
Data-to-Q delay (FO3 inverter delay)
5 6
CSE energy and delay: (a) high-V dd and (b) low-swing Clk
20% 16% 12% 8% 4% 0% 0%
N-CL N-PPL N-FF
3% 6% 9%
Noise on low-swing clock
12%
Effect of clock noise on low-swing clock latch delay
Clk Clk Clk D Clk Clk Clk Clk Clk Clk Clk DET Latch-mux circuit (Llopis and Sachdev 1996), Copyright © 1996 IEEE Q
N4 Clk N2 D N5 Clk N3 N2 Clk N4 Q N3 Clk N5 C2MOS Latch-mux (Gago et al. 1993), Copyright © 1993 IEEE
Clk Clk Clk Clk 1 Clk Clk 1 Clk 1 Clk 1 D Clk 2 Clk Clk 2 Clk (a) Clk 2 Clk 1 Clk Clk Clk Q D Clk 2 Clk Clk 1 Clk Clk 2 Clk 1 (b) Clk Clk Clk Clk 2 1 Q Pulsed-latch: (a) single - edge, (b) dual - edge triggered
1 st STAGE: X 2 nd STAGE 1 st STAGE: Y Clk D Clk 1 Clk S X S Y Q Clk Clk Clk 1 Clk 1 Clk 2 DET symmetric pulse generator flip-flop Clk D Clk 2 Clk
3 2 1 0 6 5 4 MSL/LM C2MOS-LM PL
Delay comparison, SET vs. DET
SPGFF
SE DE
180 160 140 120 100 80 60 40 20 0 Clk Non-clk MSL LM PL SE PL DE C2MOS SE C2MOS DE SPGFF
Power consumption comparison, SET vs. DET (0.18
m
m, high load)
30 20 10 0 60 50 40 M SL/LM Single Edge Double Edge C2M OS PL SPGFF
EDP comparison, single vs. dual-edge triggered clocks (0.18
m
m, high load)