Transcript ECSE 436 Signal Processing Hardware

DSP architecture
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Review of basic computer architecture
concepts
C6000 architecture: VLIW
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Principle and Scheduling
Addressing
Assembly and linear assembly
Pipelining
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DSP architecture
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Review of basic computer architecture
concepts
C6000 architecture: VLIW

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
Principle and Scheduling
Addressing
Assembly and linear assembly
Pipelining
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Instruction Set Architecture (ISA)
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Computers run programs made of simple operations
called “instructions”
The list of instructions offered by the machine is the
“instruction set”
The instruction set is what is visible to the
programmer (really the compiler, although humans
can directly program in “assembly language”)
Many different DSPs can share the same ISA but
have different hardware (i.e. the implementation of
the ISA is different)
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Instructions
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Two kinds of information in a computer:
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instructions
data
Instructions are stored as numbers, just like
data
Instructions and data are stored in the
memory
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Basic Computer Organization
CPU
Limited number
of fast registers
for temporary
storage
OPCODE
OPERANDS
registers
PC
load
Large amount
of slow memory
Arranged as an array
of bytes
store
memory
IR
Instructions are loaded into an
Instruction register (IR) from the
address pointed to by the
program counter (PC). The PC is
incremented by the instruction
size (in bytes)
for each new instruction.
E.g. PC  PC + 4
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Load/Store Architecture (Reg-Reg)
CPU
registers
• The register numbers are specified in the
operand fields of the instruction
PC
load
store
• Instructions can ONLY get their data and store
their data from/to registers.
IR
• Since data is stored in memory, we need
special “load” and “store” instructions for
transfers between registers and memory. These
two instructions are the ONLY ones allowed to
access memory
memory
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DSP architecture


Review of basic computer architecture
concepts
C6000 architecture: VLIW




Principle and Scheduling
Addressing
Assembly and linear assembly
Pipelining
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C6000 Architecture
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TMS320C62x/C64x
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TMS320C67x
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16-bit fixed point DSP
32-bit floating point DSP
Instuction set is a superset of the C62x
VLIW Architecture
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Very Long Instruction Word
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VLIW
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VLIW is an architecture that exploits
instruction level parallelism (ILP) in the code
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What is ILP?
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An instruction is dependent on another if it
uses (produces) a value produced (used) by
the other instruction
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Example
add c,d,e
mult
b,e,a
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The mult instruction
must wait for the add
instruction to finish
before it can execute
(sequential data
flow)
e
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Example
add
add
add
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a,b,e
c,d,f
e,f,g
The first two adds have no
data dependency and could
even be switched in the code
with no effect on the
correctness of the answer
The first two adds could be
executed in parallel if we had
the hardware to do it (two
adders)
a
b
d
c
+
+
e
f
+
g
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Scheduling
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Given a set of hardware resources (functional
units), e.g. a number of adders, multipliers,
etc…,
the process of determining which instructions
can be executed in parallel and which
functional units to use on any given clock
cycle is called instruction scheduling
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VLIW
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VLIW is an architecture that depends on the user
(compiler) to do the scheduling
Instructions are packed into a very long instruction
word (256 bits)
There is no scheduling hardware on the chip like on a
Pentium 4 which uses hardware, or dynamic
scheduling
Benefits
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simple hardware
Drawbacks
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requires sophisticated compilers
code compatibility – need to recompile if you use a different
DSP, even one with the same ISA
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C6713 Architecture
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Maximum Performance
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C6713
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8 functional units, two MACS per cycle
225 MHz
1800 MIPS
6 of the 8 units floating point
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225 MHz
1350 MFLOPS
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DSP architecture


Review of basic computer architecture
concepts
C6000 architecture: VLIW




Principle and Scheduling
Addressing
Assembly and linear assembly
Pipelining
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Addressing Modes
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Load/Store
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must load registers from memory, process data,
store back to memory
Linear (indirect addressing)
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32 registers A0-A15, B0-B15 can act as pointers
*R
register R contains the address of
memory location where a data value is
stored
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Linear Addressing
*R++(d)
R contains the address. After R is used,
postincrement by discplacement d
(default is d = 1), -- post decrements
*++R(d)
preincrement or predecrement
*+R(d)
preincrement without modification
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Circular Addressing
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Circular Addressing
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Address Mode Register (AMR)
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DSP architecture


Review of basic computer architecture
concepts
C6000 architecture: VLIW




Principle and Scheduling
Addressing
Assembly and linear assembly
Pipelining
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TMS320 Assemby Language
[label][:]
mnemonic [operand list] [;
comment]
[x] means that x is optional
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label
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mnemonic
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symbolic name for the address of the program line
instruction, assembler directive, macro
cannot start in column 1
operands
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constants: binary (e.g. 010101b), decimal, hexdecimal (e.g. 0x9f or 9fh)
register names
symbols defined by assembler directives
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Assembler Directives
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The assembler produces COFF (commonobect file format) files
COFF files are divided into sections that
contain instructions or data
Assembler directives are instructions to the
assembler on how to manipulate these
sections or to define constants
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they are not machine instructions
see Section 4.1 in the text for more details
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C6000 ISA
functional unit
conditional execution
parallel
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Instruction Packing
VELOCITI: 1 to 8 execute packets in a fetch packet
Instruction
Instruction
Instruction
|| Instruction
|| Instruction
1
2
3
4
5
;
;
;
;
instructions
are executed
instructions
are executed
1 and 2
sequentially
3, 4, and 5
in parallel
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Sample Instructions
ADD .L1
A3,A7,A7
;add A3+A7->A7
SUB .S1
A1,1,A1
;subtract 1 from A1
MPY .M2
|| MPYH .M1
A7,B7,B6
A7,B7,A6
; mult 16LSBs of A7,B7->B6
; mult 16MSBs of A7,B7->A6
LDH .D2
LDH .D1
*B2++,B7
*A2++,A7
; load (B2) -> B7, inc B2
; load (A2) -> A7, inc A2
||
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Sample Instructions
Loop
MVKL .S1
MVKH .S2
SUB
[A1] B
NOP
STW
.S1
.S2
.D1
x,A4
x,A4
; move 16 LSBs of x addr->A4
; move 16 MSBs of x addr->A4
A1,1,A1
Loop
5
A3, *A7
;
;
;
;
decrement A1
branch to Loop if A1 != 0
5 NOP instructions
store A3 into (A7)
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Linear Assembly
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To effectively program a DSP using assembly
language, you need to do the scheduling by
hand!
Need to account for the number of clock
cycles each functional unit takes, etc…
Difficult, so TI has linear assembly
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you don’t have to schedule it, the compiler does it
for you
can use CPU resources without worrying about
scheduling, register allocation, etc…
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DSP architecture


Review of basic computer architecture
concepts
C6000 architecture: VLIW




Principle and Scheduling
Addressing
Assembly and linear assembly
Pipelining
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Pipelining
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Key technique to make fast CPUs
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Multiple instructions are overlapped in
execution
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E.g. Automotive assembly line
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Pipelining: principle
body (B)
1 hour
paint (P)
1 hour
Wheels (W)
1 hour
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Pipelining: principle(II)
Time (h)
Bob
0
1
2
B1
P1
W1
3
4
5
B2
P2
W2
6
2 cars / 6 hours 
1/3 car / hour
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Pipelining: principle(III)
Time (h)
Bob
Alice
Bill
0
1
2
B1
1 car / hour (3 x speedup)
B2
P1
B3
P2
W1
B4
P3
W2
B5
P4
W3
B6
P5
W4
3
4
5
6
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Pipelining: principle(IV)
COMB. LOGIC
cycle time
cycle time
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Performance Gain
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Pipelining a datapath m times can result in up
to m times improvement in cycle time
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E.g. 5-stage pipelined processor is potentially 5
times faster than an unpipelined processor
In reality, this is limited to less than m
because of restrictions in overlapping
instructions
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5-Stage RISC Pipeline
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16-Stage C6713 Pipeline
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Fetch (4 stages)
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Decode (2 stages)
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calc. address, send address, wait, receive
separate fetch packets into execute packets
Execute (10 stages)
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Different instructions require different number of
cycles to execute
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Software and I/O
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Software and I/O
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Code efficiency and programming techniques
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Loop unrolling
Software pipelining
I/O considerations
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Interrupts
DMA
Block processing
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Software and I/O
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Code efficiency and programming techniques
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Loop unrolling
Software pipelining
I/O considerations
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Interrupts
DMA
Block processing
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Code Efficiency
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Intrinsic functions
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e.g. _add2, _mpy, sadd
see TMS320C62x/C67x Programmers Guide
Packed data
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use word access to operate on 16-bit data store in
the high and low parts of a 32-bit register
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Loop Unrolling
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A loop is a compact way of representing a
repetitive sequence of instructions, but…
The loop condition test is overhead
To remove the loop overhead, unroll the loop
(make copies of the loop code)
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key way of exposing parallelism !!!
The compiler can now look across loop iterations
to find parallel instructions
parallelism increased, but so is code size
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Example
; program A: code without unrolling
MVK
4,B0
loop:
LDH
*A5++,A0
||
LDH
*A6++,A1
ADD
A0,A1,A2 ;add 4 times
…
SUB
B0,1,B0
[B0]
B
loop
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Example
; program B: code with unrolling once
MVK
2,B0
loop:
LDH
*A5++,A0
||
LDH
*A6++,A1
ADD
A0,A1,A2
…
LDH
*A5++,A0
||
LDH
*A6++,A1
ADD
A0,A1,A2
…
SUB
B0,1,B0
[B0]
B
loop
; add first 2 numbers
; add other 2 numbers
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Software and I/O
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Code efficiency and programming techniques
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Loop unrolling
Software pipelining
I/O considerations
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Interrupts
DMA
Block processing
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Software Pipelining
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Software pipelining
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compiler technique (don’t confuse with h/w
pipelining)
Schedule multiple iterations of a loop together to fill
any empty cycles and maximize functional unit
usage
-O2 –O3
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Software Pipelining
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The general idea of this optimization is to
uncover long sequences of statements without
branch statements
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Reorganize loops to interleave instructions
from different iterations
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Dependent instructions within a single loop
iteration are then separated from one another by
an entire loop body
Increases possibilities of scheduling
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Software Pipelining
Iteration
0
Iteration
Iteration
1
2
Iteration
3
Iteration
4
Soft warepipelined
it eration
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Software Pipelining
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Advantage: yields shorter code than loop
unrolling and uses fewer registers
Software pipelining is crucial for VLIW
processors
Often, both software pipelining and loop
unrolling are used
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Software and I/O
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Code efficiency and programming techniques
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Loop unrolling
Software pipelining
I/O considerations
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Interrupts
DMA
Block processing
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Interrupts
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A signal that causes the processor to suspend
its current program and execute a special
subroutine
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interrupt service routine (ISR)
Sources
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On-chip peripherals
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External
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timers, serial ports
resets, external peripherals
Software interrupts
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arithmetic exceptions (divide by zero, overflow)
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Interrupts
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Interrupts
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Interrupts
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Software and I/O
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Code efficiency and programming techniques
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Loop unrolling
Software pipelining
I/O considerations
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Interrupts
DMA
Block processing
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Direct Memory Access
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Data transfer without intervention of
processsor
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memory and CPU
peripherals and CPU
DMA channel:
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source address
destination address
element count in a frame
number of frames in a block
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Software and I/O
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Code efficiency and programming techniques
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Loop unrolling
Software pipelining
I/O considerations
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Interrupts
DMA
Block processing
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Block Processing
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Ping-Pong Buffering
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Ping-pong buffer (double buffer)
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DMA channel delivers N samples of data in
and out of buffers while the DSP operates on
data in the current buffer
Next block, roles of the buffers are changed
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