Advanced Methods for Circuit Design Hardware Design Languages
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Transcript Advanced Methods for Circuit Design Hardware Design Languages
www.ict.tuwien.ac.at
Semi-Symbolic Analysis of Analog and
Signal Processing Systems
Carna Radojicic, Florian Schupfer
and Prof. Dr. Christoph Grimm
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Overview
1. Motivation
2. State of the Art
3. Proposed Solution
4. Simulation results
5. Conclusion
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Motivation
Accurate models -> Increase in model parameters
Process variation -> Parameter deviations
Efficient system analysis and verification methods
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Motivation
Verification of analog-mixed signal systems with parameter
deviations
Achieving full coverage with small number of simulation runs
Numerical Simulation:
Semi-symbolic simulation:
• Incomplete coverage
• High number of simulation runs
• Complete coverage
for considered parameter space
• One simulation run
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State of the Art
Simulation based techniques
• Monte Carlo, Corner Case, Worst Case
• Design of Experiments[Rafaila]
• Importance sampling[Srinivasan]
Formal verification techniques
• Model checking, Equivalence checking
• Hybrid verification[Henzinger]
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Proposed solution
Parameter deviations
represented as ranges
using Affine Arithmetic
Semi-symbolic simulation
• Guaranteed result inclusion
in one simulation run
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Semi- symbolic simulation on system level – SystemC AMS
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Implementation
Simulation on transistor level
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Affine Arithmetic
System deviations modeled in intervals
Intervals labeled by symbols
Symbols εi represent interval [-1, 1]
xi is the numerical value which scales the interval
Affine variable consists of nominal value and superimposed
intervals
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Graphical representations
y(t)
y(t)
x0
x3ε3
x2ε2
x1 ε1
x1 ε1
x2ε2
x3ε3
positive
negative
t
t
Range based system response
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Signal construction by sub-ranges
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I/Q receiver with parameter deviations
I
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The bounds of output signal ranges represent the worst case behavior
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Simulation results
The principle for verification
• The system meets specification for the worst case -> The specification
is satisfied for all values included into the range
• Formal verification result obtained inside the range
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The specification for the worst case not satisfied -> the system
must be refined
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Simulation results
To refine the system the sources of uncertainties must be
tracked back to their origin to be identified
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Efficient simulation performance
Pessimistic worst case bounds single run
Traceable deviations influence
Refinement information/recommendations
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Conclusion
13 /13
Monika Rafaila, Christoph Grimm, Christian Decker, and Georg Pelz.
Sequential design of experiments for effective model-based validation of
electronic control units. e&i Elektrotechnik und Informationstechnik,
127:164–170, 2010.
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Thank You for Your Attention!
R. Srinivasan, Importance sampling - Applications in communications and
detection, Springer-Verlag, Berlin, 2002.
Darius Grabowski, Daniel Platte, Lars Hedrich, and Erich Barke. Time
Constrained verification of Analog Circuits using Model-Checking
Algorithms. Electronic Notes in Theoretical Computer Science (ENTCS),
153(3):37–52, 2006.
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