Transcript Requirements

VLVnT – Workshop 2003
Read Out and Data Transmission
Working Group
A 200-MHz FPGA based PMT
acquisition electronics for NEMO
experiment
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
VLVnT – Workshop 2003
The NEMO Km3 experiment
64 towers placed on a square grid
(8x8).
The towers are electro-optically
linked (8 by 8) to one of the 8 so
called secondary junction boxes
1400 m
(S-JB).
200 m
Tower
200 m
Secondary JB
Primary JB
The S-JBs are then connected to
the so called primary junction box
(P-JB) which links the apparatus
to the main electro-optical cable
arriving from on shore.
Main electro optical cable
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
VLVnT – Workshop 2003
The Tower
FCM
(Floor Control Module)
PMT64
20m
19.44 Mbps
PMT63
Benthosphere
DAQ
Floor 16
40m
Floor 15
40m
Floor 14
STM-1
(155 Mbps)
Floor 2
PMT4
PMT3
40m
Floor 1
Data On Fiber
2.5 Gbps
PMT1
PMT2
150m
Secondary
Junction-Box
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Tower Junction-Box
(Optical Interleaver)
VLVnT – Workshop 2003
Data acquisition electronics
benthosphere
PSU
PMT
DAQ
Board
Three twisted pairs
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Floor Control Module
VLVnT – Workshop 2003
Constraints
PMT Signal:
Bandwidth 100MHz
Output voltage range: 0  -40V
Threshold value for L0 trigger: ~ -30mV (~1/4 photoelectron for 13’’ PMT)
Single photoelectron rate (due to 40K ):
Event rate (with a 13” PMT): ~50 kevents/s
Event length: ~50ns
Electro-mechanical:
Power consumption as low as possible (long distance power transport).
Long mean time between failure (no repairing possible).
Small & simple (the fewer the components the more reliable the system).
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
VLVnT – Workshop 2003
Constraints: consequences
PMT Signal Bandwidth: 100MHz
Sampling rate: 200MHz
PMT Signal Dynamics: -40V / -30mV ~ 1300  2048 (11 bit)
Sampling resolution: 8 bit
Quasi logarithmic analog compression
DAQ Input Signal Dynamics: -40V / -18mV
Physical data rate (for a 13” PMT):
50 kevents/s X (100 bit/event) ~ 5Mbps
Sampling data rate: 200MHz X 8bit = 1.6Gbps
Thus, using a user definable digital threshold, the sampling data rate
can be reduced to the expected value of 5Mbps.
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
VLVnT – Workshop 2003
Block diagram
8 Digital I/O lines
200Msps
PMT
AFE ADC
FPGA
Pt
Temp.
Sens.
Clock in
MOD/DEM
Analog I/O
(7 in, 4 out)
+
8 ch
12 bit
DAC
8 ch
10 bit
ADC
Flash
EPROM
ssi
POWER
DSP
PTS AFE
JTAG
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Data/Control
out
RS232
Power
+
Control
VLVnT – Workshop 2003
The Analog Front End
Analog 8Front
DigitalEnd
I/O lines
PMT
- Impedence matching ( 50 Ohm )
- Passive quasi-logarithmic signal compression
200Msps
- The compression is obtained using a diode, the
charachteristic of which varies mainly with
Clock in
Pt
Temp.
temperature, which can be measured through a
Sens.
MOD/DEM
platinum temperature sensor.
- Since modelling of the characteristic +
curve of
the diode is difficult, the system self-measures Data/Control
12 bit
POWER
8 ch DAC
the compression
curve allowing onshore
data
out
Flash
EPROM
decompression
(self calibration).
AFE ADC
Analog I/O
(7 in, 4 out)
8 ch
FPGA
10 bit
ADC
ssi
PTS AFE
DSP
Two 12-bit-DACs are used to perform the
self-calibration.
JTAG RS232
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Power
+
Control
VLVnT – Workshop 2003
The Analog Front End
8 Digital I/O lines
200Msps
PMT
Analog Front End: compressor
AFE ADC
schematic
FPGA
Pt
Temp.
Sens.
Clock in
MOD/DEM
Analog I/O
(7 in, 4 out)
+
8 ch
8 ch
12 bit
DAC
Flash
10 bit
ADC
470
38
POWER
DSP
20
12
ssi
470
470
PTS AFE
- only passive components.
JTAG
RS232
- it’s possible, by
changing
the resistor’s value,
to change the compression curve.
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Data/Control
out
Power
+
Control
VLVnT – Workshop 2003
The Analog Front End: calibration curve
0
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
512
1024
VLVnT – Workshop 2003
200 Msample/s analog to digital conversion
8 Digital I/O lines
200Msps
PMT
AFE ADC
Pt
Temp.
Sens.
Analog I/O
(7 in, 4 out)
8 ch
12 bit
DAC
8 ch
10 bit
ADC
The 200Msps ADC
FPGA
To reduce power consumption
two
MOD/DEM
100MHz 8-bit differential FlashADCs are
+
used.
Data/Control
One is triggered on the 100MHz clk signal.
POWER
out
The other is triggered on the NOT(clk)
Flash
signal.
ssi
PTS AFE
Clock in
DSP
Two 12-bit-DACs are used to set the
proper offset. JTAG RS232
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Power
+
Control
VLVnT – Workshop 2003
The Auxiliary analog I/Os
8 Digital I/O lines
The auxiliary analog Inputs:
200Msps
PMT
AFE ADC
Pt
Temp.
Sens.
Analog I/O
(7 in, 4 out)
8 ch
12 bit
DAC
8 ch
10 bit
ADC
8-channel 10-bit-ADC
FPGA
- one channel is used for measuring the
temperature of the compressor
diode.
MOD/DEM
Clock in
- the other 7 channels are led to+an external
Data/Control
connector
Flash
ssi
POWER
DSP
PTS AFE
JTAG
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
out
RS232
Power
+
Control
VLVnT – Workshop 2003
The Auxiliary analog I/Os
8 Digital
I/O lines
The
auxiliary
analog Outputs:
200Msps
PMT
AFE ADC
Pt
Temp.
Sens.
8 channel 12 bit DAC
- 2 channels are used for self-calibration
FPGA
Clock in
- 2 channels are used for adjusting
the offset
MOD/DEM
of the two 100 Msps differential ADCs.
Analog I/O
(7 in, 4 out)
+
8 ch
12 bit
DAC
8 ch
10 bit
ADC
- other 4 channels are led to an external Data/Control
POWER
out
connector
Flash
ssi
DSP
PTS AFE
JTAG
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
RS232
Power
+
Control
VLVnT – Workshop 2003
The DSP
The DSP:
8 Digital I/O lines
- wake-up (reads the flash memory)
- loads the FPGA bitstream
200Msps
PMT the threshold settings
- controls
- generates the 100MHz clock (PLL)
Pt
- controls the auxiliary
Temp. analog I/O (offset, selfcalibration) via SSISens.
- JTAG (debug)
- RS232 (for debug and/or instrumentation control)
AFE ADC
Analog I/O
(7 in, 4 out)
8 ch
12 bit
DAC
8 ch
10 bit
ADC
FPGA
Flash
ssi
MOD/DEM
+
POWER
Data/Control
out
DSP
PTS AFE
JTAG
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Clock in
RS232
Power
+
Control
VLVnT – Workshop 2003
The MOD/DEM block
The MOD/DEM:
8 Digital I/O lines
Connects the Board to the host
200Msps
PMT- receives Clock signal
(1.215 MHz)
AFE ADC
FPGA
- receives control signals
Pt
(45
* 9.6kbps = 432 kbps)
Temp.
Sens.
- sends data and control signals (19.44 Mbps)
- receives power (5 VDC)
Analog I/O
(7 in, 4 out)
8 ch
10 bit
ADC
ssi
POWER
Data/Control
out
DSP
PTS AFE
JTAG
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
MOD/DEM
+
bit
All connections
are 12
electric
(3 twisted pairs).
8 ch
Flash
DAC
EPROM
Clock in
RS232
Power
+
Control
VLVnT – Workshop 2003
The FPGA
8 Digital I/O lines
200Msps
PMT
AFE ADC
FPGA
Pt
Temp.
Sens.
-
Analog I/O
(7 in, 4 out)
The FPGA:
connections:8 ch
Clock in
MOD/DEM
+
12 bit
DAC
Flash
EPROM
10 bit
chfast
200 MBps from 8the
ADC ADCs
~1MBps to/from the DSP
19.44 Mbps to the
MOD/DEM
PTS AFE
432 kbps from the MOD/DEM
ssi
POWER
DSP
JTAG
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Data/Control
out
RS232
Power
+
Control
VLVnT – Workshop 2003
Inside the FPGA:
8 Digital I/O lines
block diagram
Data out
ADC
FIFO
SOC
Packet
formatter
Slow Control Data
SOC
Prog.
trigger
Time
Register
TR Reset
PMT cal
time calibration
&
command parser Slow Control
&
Timing
Slow Control Commands
97.2 MHz
From
DSP PLL
decoder
DSP Bus
DSP
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
1.215MHz
To DSP
PLL
1.215MHz
Clock
FPGA
MOD/DEM
ADC
Data (PMT +
Slow Control)
Data from PMT
VLVnT – Workshop 2003
Inside the FPGA:
The 100Mhz clock generation
ADC
SOC
SOC
Data out
Data from PMT
Data (PMT +
Slow Control)
- 1.215 MHz is generated by
the FCM
Packet
(19.44MHz / 16)
formatter
- 97.2 MHz square wave is obtained
Slow Control
PMT cal
from the DSP PLL (1.215
* 80)Data
- the sampling frequency is obtained
time calibration
using both (rising & falling) edges of the
&
Prog.
97.2MHz
square
wave
clock
signal.
Time
trigger
command parser
Register
TR Reset
Slow Control
&
Timing
Slow Control Commands
97.2 MHz
From
DSP PLL
decoder
DSP Bus
DSP
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
1.215MHz
To DSP
PLL
1.215MHz
Clock
FPGA
MOD/DEM
ADC
FIFO
8 Digital I/O lines
VLVnT – Workshop 2003
Inside the FPGA:
The FIFO and the threshold
ADC
FIFO
SOC
Data out
Data
(PMT
+ L0 trigger
- the threshold value
for
the
Data from PMT
Slow Control)
can be changed at runtime by the user.
Packet samples are stored in
- some pretrigger
formatter
the FIFO as
well as the timestamp of
the threshold
time PMT cal
Slow Control Data
SOC
Prog.
trigger
Time
Register
TR Reset
time calibration
&
command parser Slow Control
&
Timing
Slow Control Commands
97.2 MHz
From
DSP PLL
decoder
DSP Bus
DSP
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
1.215MHz
To DSP
PLL
1.215MHz
Clock
FPGA
MOD/DEM
ADC
8 Digital I/O lines
VLVnT – Workshop 2003
Inside the FPGA:
The packet parser/formatter
ADC
FIFO
SOC
Data out
Packet
formatter
Slow Control Data
SOC
Prog.
trigger
97.2 MHz
From
DSP PLL
Time
Register
decoder
DSP Bus
DSP
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
Data (PMT +
Slow Control)
Data from PMT
PMT cal
time calibration
&
Slow Control
command
parser
collects
data
from
the
FIFO
&
TR Reset
Timing
(PMT data) and data from
the
DSP (slow control data)
Slow Control Commands
- creates the bitstream to be
1.215MHz
sent to the FCM
1.215MHz
Clock
To DSP
PLL
FPGA
MOD/DEM
ADC
8 Digital I/O lines
VLVnT – Workshop 2003
Inside the FPGA:
The packet parser/formatter
8 Digital I/O lines
SOC
For example: for the measurement of the
PMT latency time a Prog.
LED can be controlled
Time
trigger
by one of the 8 digital
I/O.
Register
- Other commands are directly sent to the
DSP.
97.2 MHz
From
DSP PLL
decoder
DSP Bus
DSP
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
TR Reset
Data out
time calibration
&
command parser Slow Control
&
Timing
Slow Control Commands
1.215MHz
To DSP
PLL
1.215MHz
Clock
FPGA
MOD/DEM
- It’s fed with the slow control data
stream.
Data (PMT +
Data
from
PMT
Slow Control)
ADC
- It “recognizes” and executes the
time
FIFO
calibration
commands.
Packet
SOC
formatter
These commands have to be executed by
hardware (to be software delay free).
ADC
Slow Control Data
PMT cal
VLVnT – Workshop 2003
The protoype
Characteristics:
FPGA: Xilinx XC4028XLA
DSP: Motorola DSP56303
100Msps ADCs: AD9283
Physical dimensions:
2 x (10 cm) x (10 cm)
Power consumption:
~950mW
DAQ
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003
MOD/DEM
+
HVPSU
VLVnT – Workshop 2003
Flexibility towards the Km3
- The allocated bandwidth of the output data channel is overdimensioned compared to the physical one.
Thus, by changing the FPGA firmware, it’s possible to allocate different data
bandwidth.
- The number of auxiliary channels is reduntant.
Probably, for the NEMO Km3 we won’t need all the 7 A/D channels, 4 D/A
channels, 8 digital I/O lines, reducing number of components, power
consumption, and physical dimension.
- Using newer FPGA, it’s possible to implement the DSP functions
inside the FPGA, reducing dimensions, power consumption, costs.
Goal: power consumption < 500mW
C. A. Nicolau – VLVnT - Amsterdam 5-8 October 2003