Transcript Document

A 3Gbps/30K-Rule Virus-Detection Processor Embedded with
Adaptively Dividable Dual-Port BiTCAM for Mobile Devices
>1Gbps
PC >150K viruses
1000M
Mainframe
802.11n
100M
4G
LTE
802.11a
WiMax
(75M)
802.11b
10M
WiFi
HSDPA
3G
CDMA
Virus Count
Data Rate (bps)
100K
802.11g
10K
More than
20K viruses
Desktop
Laptop
400
viruses
1K
1M
100
2G
GSM
1990
Handtop
GPRS
2000
2008
1960
1980
2000 2008
 People can easily get information from internet through the mobile
devices
 Through high-speed wireless transmission protocols
 Growth of virus on mobile devices will be same as PCs
 Detecting viruses is a power-consumption task
 A hardware for virus detection is required
 High throughput
 Low power
 Low cost & high flexibility
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The Proposed Virus-Detection Processor
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Port2
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Port1
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Signature Table
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Input
String
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Single-port
TCAM
(8KB)
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Shift Table
(no-plane)
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Filter/EM
LSB
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Single-port
TCAM
(8KB)
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AHB Wrapper
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Filtering Engine
32-bit
Exactly- 128
Matching
Controller
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Workload > 80%
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8MB DRAM
(Suffix Tree)
1-step 32
Hash
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Controller
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Next Address
Generator
Payload Address for
Exactly-Matching
Generator
Comparator
Shift
Controller
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Serial-to-Parallel
LSB
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Shift-SRAM
(0.5KB)
MSB
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1-hot Code Generator
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Adjustable division line
no-plane
yes-plane
16-Byte FF-based Payload Buffer
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Signature-SRAM
(8KB)
Proposed BiTCAM
pointer
Result Address Generator
Pointer
Generator
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0
Filter/EM
Input String
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Exact-Match
Engine
Workload < 20%
Output Result
AHB Bus
 Virus detection is split into two phases and support new modified
algorithms by hardware
 Filtering Engine: handle >80% input data
 By Fast shit table 1
 By Signature filtering 2
 Exact-Matching Engine: <20% data need to be precisely checked
 By efficient Trie Tree 3
 On-chip memory dominates the power and area
 Proposed BiTCAM reduces them by merging two algorithm’s data
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Chip Micrograph and Features
 Contribute a high-performance, low-power and low-cost
virus-detection processor
 Support 3Gbps real-time virus detection for mobile devices.
 Handle 30,000 ClamAV viruses
Search and Write Buffer
Wrapper and BIST
Controller
1798μm
0.13µm 1P8M Mixed
Signal CMOS Process
Core Supply Voltage
1.2V
I/O Supply Voltage
3.3V
Rule Count
ClamAV 30,000
On-chip Memory Size
1366μm
1798μm
Bank3
Bank2
Bank1
Bank0
BiTCAM+SRAM
1612μm
Technology
8KB BiTCAM+
8.5KB SRAM
CAM cell area/bit
6.238μm×2.440μm
On-chip Memory Area
1.366mm×1.612mm
Core area
1.798mm×1.798mm
Processor*
Power
131.22mW
Controller*
28.04mW
Wrapper*
20.72mW
Memory*
82.46mW
Simulated Clock Freq.
380MHz
Measured Clock Freq.
380MHz
Throughput
3.04Gbps
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